Lecture on "Design Verification Using TestBench"

#Design #Verification #Verilog #Functinality #TestBench
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A session was conducted by K.Swetha Reddy Assistant Professor of VNR VJIET on TestBench in Verilog HDL on 24th June 2020 from 11AM to 1PM.

The session was started by discussing regarding the functionality design i.e., how it should be functionally correct and how to achieve the desired output. Further the speaker talks about how we can generate the test vectors or input combinations to a design so that it can be tested as efficiently as possible. Then, the advantages of TestBench was explained and how we can generate values for input combinations. The design of TestBench and the concept of Programming language Interface(PLI) was explained in detail.

The speaker also explained about TestBench-Half Adder, TestBench for 2XI MUX and gave related examples about it. Designing of initial block, how the stimulators work, how verilog’s compiler will treat the statements all these concepts were explained in detail with examples.


  Date and Time

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  • Date: 24 Jun 2020
  • Time: 11:00 AM to 01:00 PM
  • All times are (UTC+05:30) Chennai
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  • Hyderabad, Andhra Pradesh
  • India
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  Speakers

Ms K Swetha Reddy

Biography:

Assistant Professor at VNR VJIET.




Agenda

To learn regarding the Design Verification of TestBench in Verilog HDL and to check the functionality design. All the concepts were explained clearly and was understood by the students.


A total of 45 students attended the session and utilized this lockdown time to learn something new and get knowledge about Machine learning and learn the concept of TestBench.


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SS 2 24.36 KiB
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