Another Inconvenient Truth: Snails Are More Intelligent Than Us


For decades there has been a new CMOS technology node approximately every two years. Until recently, thanks to scaling, the key feature of every new technology node has been a 100% integration capacity and 40% performance improvement… free-of-charge. The International Technology Roadmap for Semiconductors (ITRS) has been architected in such a way that this improvement became a self-fulfilling prophecy of the roadmap itself. Everything else has been bent in the attempt to make scaling happen… forever. That has changed as we approach the near end of Moore’s Law. 

For eons snails have built the cells of their shell according to the Fibonacci’s numbers – where each cell has a volume that is the sum of the volume of the previous two cells. Snails understand, however, that at a certain point in time growth must stop to prevent the collapse of the shell by making it too big and therefore fragile. When this point is reached, snails do stop adding larger cells, and start improving the robustness of the shell.

Back to us: technology-wise, scaling has rapidly exhausted the resources of CMOS technology, which, by now, struggles to deliver any further improvement. A number of fundamental challenges have emerged, both technical and financial, which force a thorough rethinking of how scaling has been done, and whether scaling continues to be the most appropriate solution to provide the world with the silicon content that it needs.

Like Al Gore’s premise on energy consumption and global warming, there is an inconvenient truth to be acknowledged in our industry: scaling is like fossil fuels – the cheapest and easiest way to go. Unfortunately, also like fossil fuels, it is not sustainable indefinitely. And it becomes more costly and inefficient every day. New avenues, which are available today, are worth exploring and must be undertaken. That is, unless snails are more intelligent than us…

In this talk, Dr. Williams will describe the problems with scaling and a number of possible solutions, including the latest alternative paths and their relative merits.


Dr. Thomas W. Williams is a retired Synopsys Fellow at Synopsys in Boulder, Colorado, U.S.A, currently living in Canmore, AB, Canada. Formerly, he was with IBM Microelectronics Division and manager of the VLSI Design for Testability group. He received a B.S.E.E. from Clarkson University, an M.A. in pure mathematics from the State University of New York at Binghamton, and a Ph.D. in electrical engineering from Colorado State University. Dr. Williams was named an IEEE Fellow in 1988 and received the Computer Society's W. Wallace McDowell Award for outstanding contributions to the computer art in 1989. In 2018 he received the Phil Kaufman Award, “The Nobel Prize” of Semiconductor Industry.

  Date and Time




Virtual session information will be sent to registrants the day before the event.

  • Starts 22 October 2020 11:55 PM
  • Ends 11 November 2020 11:59 PM
  • All times are America/Edmonton
  • No Admission Charge
  • Register