High-Speed CMOS Serial Transmitters for 56-112Gb/s Electrical Interconnects

#CMOS #Transmitters
Share

Abstract: Data rates in high-speed wireline communication links continue to increase, fueled by demands in
data center and high-performance computing applications. In recent years, serial link data rates have
increased from 28Gb/s to 56Gb/s, with 112Gb/s rapidly approaching. To achieve these higher data rates
across high-loss electrical channels, standards are switching from NRZ to PAM4 signaling. In this talk, we
will start with an overview of serial transmitter architectures focusing on feed-forward equalization (FFE)
techniques as well as power considerations for PAM4 links. Next, we will look at the design of a 56-Gb/s
PAM4 transmitter designed in 14nm FinFET CMOS technology with a fractionally-spaced FFE. Finally we
will look at directions for 112Gb/s and discuss the design of a 112-Gb/s PAM4 transmitter in 14nm FinFET
CMOS technology with precise equalization control to minimize intersymbol interference in PAM4 links.


  Date and Time

  Location

  Hosts

  Registration


  • Date: 23 Nov 2020
  • Time: 04:30 PM to 05:30 PM
  • All times are (GMT-05:00) US/Eastern
  • Add_To_Calendar_icon Add Event to Calendar
If you are not a robot, please complete the ReCAPTCHA to display virtual attendance info.
  • Contact Event Host

  • Shubha Bommalingaiahnapallya
    shubha.bpallya@gmail.com

    Kaushik Sengupta

    kaushiks@princeton.edu


  Speakers

Timothy O. (Tod) Dickson, Ph.D. of IBM T.J. Watson Research Center

Biography:

Timothy (Tod) Dickson received the B.S. and M.Eng. degrees at the University of Florida, and the Ph.D.
degree at the University of Toronto. Since 2006, he has been with the IBM T.J. Watson Research Center in
Yorktown Heights, NY. He currently leads research projects investigating high-speed power-efficient I/O
solutions for electrical and optical wireline communication links. He is also an Adjunct Professor at Columbia
University in New York, NY, where he teaches graduate courses in analog and mixed-signal circuit design.
He has received numerous best paper awards, including the IEEE Journal of Solid-State Circuits Best Paper
Award in 2009, and the IEEE Custom Integrated Circuits Conference (CICC) Best Paper Award in 2015. He
is an Associate Editor for the IEEE Solid State Circuits Letters, and serves on the Technical Programming
Committee of the IEEE CICC. He is a Senior Member of the IEEE, and a Solid State Circuits Society
Distinguished Lecturer for 2019-2020.