Circuits and Architectures for Computation with Ultra-Wide Power-Performance Adaptation - Well Beyond Voltage Scaling

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Wide power-performance adaptation is becoming crucial in always-on nearly real-time and energy-autonomous integrated systems that are subject to wide variability in the power availability and the performance target. Adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of a new breed of integrated systems having an extremely wide performance-power scalability and adaptation, beyond conventional voltage scaling or adaptive parallelism. In this talk, new techniques that drastically extend the performance-power scalability of digital circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path. Adaptation to a very wide range of energy/power availability is also discussed, presenting demonstrations of always-on systems (e.g., microcontrollers, power management units) with power down to sub-nW, and duty-cycled operation down to pW range. Several silicon demonstrations are illustrated to quantify the benefits offered by wide power-performance adaptation, and identify opportunities and challenges for the decade ahead.



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  • Date: 16 Dec 2020
  • Time: 07:00 PM to 08:30 PM
  • All times are America/New_York
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  • San Diego
  • United States



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Circuits and Architectures for Computation with Ultra-Wide Power-Performance Adaptation - Well Beyond Voltage Scaling

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Abstract:Wide power-performance adaptation is becoming crucial in always-on nearly real-time and energy-autonomous integrated systems that are subject to wide variability in the power availability and the performance target. Adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of a new breed of integrated systems having an extremely wide performance-power scalability and adaptation, beyond conventional voltage scaling or adaptive parallelism. In this talk, new techniques that drastically extend the performance-power scalability of digital circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path. Adaptation to a very wide range of energy/power availability is also discussed, presenting demonstrations of always-on systems (e.g., microcontrollers, power management units) with power down to sub-nW, and duty-cycled operation down to pW range. Several silicon demonstrations are illustrated to quantify the benefits offered by wide power-performance adaptation, and identify opportunities and challenges for the decade ahead.

Bio: Massimo Alioto is a Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, and is the Director of the Integrated Circuits and Embedded Systems area and the FD-FAbrICS research center on intelligent&connected systems. He held positions at the University of Siena, Intel Labs CRL, University of Michigan Ann Arbor, University of California Berkeley, EPFL - Lausanne.

He is (co)author of 300 publications on journals and conference proceedings, and four books with Springer. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies.

He is the Editor in Chief of the IEEE Transactions on VLSI Systems, Distinguished Lecturer for the IEEE Solid-State Circuits Society, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012), as well as Distinguished Lecturer (2009-2010) and member of the Board of Governors (2015-2020). He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2023, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.
 

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