#Versal #ACAP #adaptive #SoCs #Domain #Specific #Architectures #that #are #scalable #and #optimized #to #meet #a #wide #range #of #application #requirements...

When and How
Date: January 27th, 2021
Time: 4:00 pm – 5:00 pm Eastern Time
Location: Saint Maurice, Trois Rivieres, Quebec, CANADA
Meeting ID: 896 8645 0185
Password: 008577


The Versal ACAP is a new platform offering from Xilinx that exploits leading edge 7nm semiconductor process technology with semiconductor innovation to create a new category of adaptive SoCs. This portfolio of devices can be used to create Domain Specific Architectures that are scalable and optimized to meet a wide range of application requirements from end points to vehicles to infrastructure. 5G architectures requiring compute intensive functionality, such as massive MIMO and beamforming, are key target applications that are enabled by Versal and its’ silicon innovations.
Tools are a critical component of enabling the developer community to leverage the full potential of Versal platforms. Vitis Unified Software Platform, combined with Vivado Design Suite, offers a comprehensive development environment and programming model that enables all developers, including hardware and software engineers, and data scientists to access the full potential of Versal ACAP. With Vitis, developers can meet the growing challenges and unique requirements of their applications, while continuing to work at an application level and develop in familiar programming languages & frameworks.
In this session, equal time will be spent reviewing the benefits and features of both Versal devices and the Vitis tool flow with an emphasis on 5G applications.

  Date and Time




  • Date: 27 Jan 2021
  • Time: 04:00 PM to 05:00 PM
  • All times are (GMT-05:00) America/Montreal
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  • 3351 Boulevard des Forges,
  • Trois Rivieres, Quebec
  • Canada G9A 5H7

  • Contact Event Hosts
  • Starts 18 January 2021 08:00 AM
  • Ends 27 January 2021 04:00 PM
  • All times are (GMT-05:00) America/Montreal
  • No Admission Charge
  • Menu: Family Name, Given Name, Occupation, E-mail address, Are you IEEE member?


Ms. Uttara Kumar Ms. Uttara Kumar of Xilinx


The VERSAL ACAP XILINX’s new platform


Ms. Uttara Kumar: Sr. Product Marketing Manager
Ms. Uttara Kumar is a Sr. Product Marketing Manager for Vitis Unified Software Platform and works on evangelizing the Software and AI inferencing solutions at Xilinx. She is passionate about enabling all developers to tap into the world of Xilinx FPGA acceleration and cares deeply about democratizing access to technology for everyone and accelerating the pace of innovation. She has a Master's degree in Electrical Engineering from the University of Michigan, Ann Arbor and prior to joining Xilinx, helped grow the adoption of MATLAB & Simulink in the areas of signal processing, communications and parallel computing at MathWorks.

Mr. Josh Sullivan Mr. Josh Sullivan of Xilinx


The VERSAL ACAP XILINX’s new platform


Mr. Josh Sullivan, Product Line Manager
Mr. Josh Sullivan is the Product Line Manager for the Zynq UltraScale+ RFSoC, Virtex, and Kintex evaluation board product lines and is responsible for managing both new product introduction as well as mature product maintenance. Josh has a background in the telecommunication’s test & measurement industry including holding roles directly dealing with ethernet, WiFi, cable access, and fiber optic solutions. Josh holds a Bachelor’s degree in Electrical Engineering from Santa Clara University.