A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS

#SerDes #XSR #Wireline #High-speed
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In this talk, Rambus will review their recent 26.5625Gbps to 106.25Gbps XSR SerDes macro in 7nm CMOS. The talk will go over the system architecture, self-test features, and measurement results. A 1.55pJ/b power efficiency and beachfront density of 722Gbps/mm have been achieved.


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  • Date: 28 Jan 2021
  • Time: 04:10 PM to 05:00 PM
  • All times are (GMT-05:00) US/Eastern
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  • Starts 20 January 2021 09:00 PM
  • Ends 28 January 2021 09:00 PM
  • All times are (GMT-05:00) US/Eastern
  • No Admission Charge

  Speakers

Ravi Shivnaraine of Rambus

Biography:

Mr. Shivnaraine obtained his Bachelors and Masters from the University of Toronto in 2010 and 2012 respectively. Ravi has experience working on SerDes receivers at Snowbush, Huawei, and Rambus at 28Gbps, 56Gbps, and 112Gbps. Currently, he is at AnalogX working on next-generation SerDes in deep sub-micron nodes. His research interests are low power SerDes interfaces and digitally assisted analog techniques.