A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS

#SerDes #XSR #Wireline #High-speed
Share

In this talk, Rambus will review their recent 26.5625Gbps to 106.25Gbps XSR SerDes macro in 7nm CMOS. The talk will go over the system architecture, self-test features, and measurement results. A 1.55pJ/b power efficiency and beachfront density of 722Gbps/mm have been achieved.


  Date and Time

  Location

  Hosts

  Registration


  • Date: 28 Jan 2021
  • Time: 09:10 PM UTC to 10:00 PM UTC
  • Add_To_Calendar_icon Add Event to Calendar
If you are not a robot, please complete the ReCAPTCHA to display virtual attendance info.
  • Contact Event Host
  • Starts 21 January 2021 02:00 AM UTC
  • Ends 29 January 2021 02:00 AM UTC
  • No Admission Charge

  Speakers

Ravi Shivnaraine of Rambus

Biography:

Mr. Shivnaraine obtained his Bachelors and Masters from the University of Toronto in 2010 and 2012 respectively. Ravi has experience working on SerDes receivers at Snowbush, Huawei, and Rambus at 28Gbps, 56Gbps, and 112Gbps. Currently, he is at AnalogX working on next-generation SerDes in deep sub-micron nodes. His research interests are low power SerDes interfaces and digitally assisted analog techniques.