IEEE SWISS SSC DISTINGUISHED LECTURE (WEBINAR) / IC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD

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Dear Members,

We hope all of you are doing well and healthy.

Your Swiss Solid State Circuit Society chapter is please to host Prof. Makoto Nagata from Kobe University.

The video conferencing link will be provided on the day to registred attendees.

The topic of the lecture is : " IC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD "

Please Join at 9:00 AM [CET] mute your headset or microphone.

We make a group picture in the begining for society report.

For the Q&A make sure to have your headset or a proper microphone.

The Agenda is as follow:

09:00 - 09:05 Welcome participants Teleconference set-up

09:05 - 9:50 Lecture

09:50 - 10:15 Questions / Discussion

We look forward meeting you and having fruitful discussion.

Kind regards,

Mathieu Coustans for your IEEE Switzerland Solid State Circuit Society committee.



  Date and Time

  Location

  Hosts

  Registration



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  • Zurich
  • Switzerland

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  • As we happend to be in Region 8 time zone, we kindly invite SSCs members of the region to join online.

  • Starts 26 March 2021 12:04 PM
  • Ends 21 April 2021 11:00 PM
  • All times are Europe/Zurich
  • No Admission Charge


  Speakers

Makoto Nagata

Makoto Nagata of University of Kobe

Topic:

IC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD

Interactions of IC chips and packaging structures differentiate the electronic performance of power delivery networks (PDNs) in traditional 2D and advanced 2.5D and 3D technologies. This presentation discusses their impacts on signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC) and electrostatic discharge protection (ESD), through in-depth Si experiments with in-place noise measurements and full-chip level noise simulations. Test vehicles under study are given in traditional 2D face up and flip chip packaging, 2.5D fan-out wafer level packaging (FOWLP), and 3D chip stacking with through silicon vias (TSVs).

Biography:

Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, in 1991 and 1993, respectively, and a Ph.D. in electronics engineering from Hiroshima University, Hiroshima, in 2001. He was a research associate at Hiroshima University from 1994 to 2002, an associate professor at Kobe University from 2002 to 2009 and promoted to a full professor in 2009. He is currently a professor of the graduate school of science, technology and innovation, Kobe University, Kobe, Japan. He is a senior member of IEICE and IEEE.

His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety.

Dr. Nagata has been a member of a variety of technical program committees of international conferences such as the Symposium on VLSI Circuits (2002-2009), Custom Integrated Circuits Conference (2007-2009), Asian Solid-State Circuits Conference (2005-2009), International Solid-State Circuits Conference (2014-2017), European Solid-State Circuits Conference (2020-) and many others. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-present). He is also serving as SSCS AdCom member (2020-). He is currently an associate editor for IEEE Transactions on VLSI Systems (2015-present). He was a technical program chair (2010-2011), a symposium chair (2012-2013) and an executive committee member (2014-2015) for the Symposium on VLSI circuits, and also a chair for IEEE SSCS Kansai Chapter (2017-2018).