Wafer-Scale Heterogeneous Integration

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Silicon interconnect fabric (Si-IF) promotes a paradigm shift in ultra-large-scale heterogeneous integration. The Si-IF is a wafer-scale platform that supports integration of heterogeneous bare (unpackaged) dies. The dies are connected using fine pitch vertical interconnects (pillars) designed directly on the Si-IF, effectively eliminating the need for package and printed circuit board. The pitch of the vertical pillars that are used to bond dies to the Si-IF is 2 to 10 μm, and the minimal distance between adjacent dies on the Si-IF is approximately 50 μm. The Si-IF supports SoC-like integration at a wafer level, enabling scaled out applications that were previously not practical (e.g., neuromorphic systems).

 

To enable the Si-IF as a practical platform for ultra-large-scale heterogeneous integration, system-level design challenges must be addressed. Borrowing from a network-on-chip (NoC), a network on interconnect fabric (NoIF) is proposed to support global communication on the Si-IF. Unlike NoCs, the NoIF is expected to provide additional system-level services, including power management, synchronization, and testing (built-in self-test) on the Si-IF. The Si-IF is a passive platform; utility dies (UDs) serve, therefore, as intelligent nodes within the NoIF to support all of the services that the network provides.



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  • Date: 22 Apr 2021
  • Time: 11:00 AM to 12:00 PM
  • All times are (GMT-05:00) America/Montreal
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  • Co-sponsored by STARaCOM
  • Starts 29 March 2021 09:39 AM
  • Ends 22 April 2021 11:00 AM
  • All times are (GMT-05:00) America/Montreal
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  Speakers

Boris Vaisband, PhD, Assistant Prof., McGill University Boris Vaisband, PhD, Assistant Prof., McGill University

Topic:

Wafer-Scale Heterogeneous Integration

Silicon interconnect fabric (Si-IF) promotes a paradigm shift in ultra-large-scale heterogeneous integration. The Si-IF is a wafer-scale platform that supports integration of heterogeneous bare (unpackaged) dies. The dies are connected using fine pitch vertical interconnects (pillars) designed directly on the Si-IF, effectively eliminating the need for package and printed circuit board. The pitch of the vertical pillars that are used to bond dies to the Si-IF is 2 to 10 μm, and the minimal distance between adjacent dies on the Si-IF is approximately 50 μm. The Si-IF supports SoC-like integration at a wafer level, enabling scaled out applications that were previously not practical (e.g., neuromorphic systems).

 

To enable the Si-IF as a practical platform for ultra-large-scale heterogeneous integration, system-level design challenges must be addressed. Borrowing from a network-on-chip (NoC), a network on interconnect fabric (NoIF) is proposed to support global communication on the Si-IF. Unlike NoCs, the NoIF is expected to provide additional system-level services, including power management, synchronization, and testing (built-in self-test) on the Si-IF. The Si-IF is a passive platform; utility dies (UDs) serve, therefore, as intelligent nodes within the NoIF to support all of the services that the network provides.

Biography:

 

Boris Vaisband is currently an Assistant Professor at the Electrical and Computer Engineering Department, McGill University, Montreal, QC, Canada. He received a B.Sc. degree in Computer Engineering from the Technion – Israel Institute of Technology, Haifa, Israel in 2011, and an M.S. and Ph.D. degrees in Electrical Engineering from the University of Rochester, Rochester, NY, in, respectively 2012 and 2017. From 2017 to 2019, he was a Postdoctoral Scholar at the University of California, Los Angeles. Previously, between 2008 and 2011, he held a hardware design position at Intel Corporation in Israel. In the summer of 2013, he interned with the Optical and RF research group at Cisco Systems Inc., San Jose, CA. In the summer of 2015, he interned with the Power Design team at Google Inc., Mountain View, CA. In 2021, Boris received the Peter Silvester Faculty Research Award. His current research interests are in integration and design methodologies for heterogeneous systems, including power delivery, communication, thermal aware design and floorplanning, and noise coupling. Some applications of interest are ultra-large-scale artificial intelligence systems, high performance computing, Internet of Things, and bio-compatible devices.