Nonvolatile Memories for Hardware Security: From OTP (One-time-programming) to PUF(Physical Unclonable Function)

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Encryption, security, functionality and identification setting become indispensable in the IoT and the upcoming 5G era for high-end consumer electronics. As a result, various SoC applications bring up an increasing demands of logic memory IP in advanced technology nodes. Comparing to the stand-alone memory chips (NAND, NOR flash), the development of specific function of memory, such as One-Time-Programming or PUF(Physical Unclonable Function), becomes more popular in terms of its simplicity based on the pure logic process.

In this talk, a non-volatile OTP memory cell, using a specific dielectric breakdown, named dFuse, discovered as a third breakdown different from conventional soft-breakdown and hard-breakdown, has been able to achieve high density and excellent data storage, for reliable and high security applications. Based on the device physics, the mechanism of the dielectric breakdown will first be introduced and the origin of the breakdown will be described. Its applications which led to the further development of OTP cell design and macro chips will also be demonstrated. Further implementation as a PUF will then be demonstrated. In particular, the opportunities and challenges on the current 28nm HKMG generations and beyond will be addressed.



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  • Date: 21 Jun 2021
  • Time: 06:30 PM to 07:30 PM
  • All times are Australia/Victoria
  • Add_To_Calendar_icon Add Event to Calendar
  • Melbourne, Victoria
  • Australia 3000

  • Starts 11 April 2021 01:08 AM
  • Ends 03 June 2021 12:00 PM
  • All times are Australia/Victoria
  • No Admission Charge


  Speakers

Professor Steve Chung

Professor Steve Chung of Chair Professor at National Yang Ming Chiao Tung University (NYCU), Taiwan

Topic:

Nonvolatile Memories for Hardware Security: From OTP (One-time-programming) to PUF(Physical Unclonable Function)

Encryption, security, functionality and identification setting become indispensable in the IoT and the upcoming 5G era for high-end consumer electronics. As a result, various SoC applications bring up an increasing demands of logic memory IP in advanced technology nodes. Comparing to the stand-alone memory chips (NAND, NOR flash), the development of specific function of memory, such as One-Time-Programming or PUF(Physical Unclonable Function), becomes more popular in terms of its simplicity based on the pure logic process.

 

In this talk, a non-volatile OTP memory cell, using a specific dielectric breakdown, named dFuse, discovered as a third breakdown different from conventional soft-breakdown and hard-breakdown, has been able to achieve high density and excellent data storage, for reliable and high security applications. Based on the device physics, the mechanism of the dielectric breakdown will first be introduced and the origin of the breakdown will be described. Its applications which led to the further development of OTP cell design and macro chips will also be demonstrated. Further implementation as a PUF will then be demonstrated. In particular, the opportunities and challenges on the current 28nm HKMG generations and beyond will be addressed.

Biography:

STEVE CHUNG received his Ph.D. degree from the University of Illinois at Urbana- Champaign, in Electrical Engineering.

Currently, he is a Chair Professor and UMC Research Chair Professor at the National Yang Ming Chiao Tung University (NYCU).  He was a visiting professor with Stanford University (2001, 2009), University of California-Merced (2009-2010), giving course lectures at both universities in the Fall of 2009.  He has also been a consultant of the two world largest IC foundries, TSMC and UMC. His current research areas include- Nanoscale CMOS device physics and technology; flash memory technology and reliability; and reliability physics and interface characterization, In-memory Computing for AI. He has published more than 300 journal and conference papers, one textbook, and holds about 40 patents. Since 1995, he presented more than 30 times in the world leading IEEE conferences, IEDM and VLSI. In particular, he is the first (from Taiwan) to present the paper at VLSI Technology symposium in 1995.

 

He is an IEEE Fellow, a distinguished Lecturer of IEEE, and has ever served as Board of Governor of EDS for 12 years. Prior involvements include: EDS Regions/Chapters Vice-Chair/Chair, and Editor of J-EDS, Editor of EDL. He has served in the TPC of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, SNW, VLSI-TSA etc. Among numerous award he received includes: 3 times outstanding research awards, distinguished PI, and distinguished NSC Research Fellow, from the National Science Council; Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research; a Lifetime Achievement Award of National Inventors. He was also granted Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan.

Email:

Address:Taipei, Taiwan