An 8 Gb GDDR6X DRAM Achieving 22 Gb/s/pin with Single-ended PAM-4 Signaling

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Several factors drive the demand for DRAM bandwidth scaling: in addition to established applications in visualization, there has been a proliferation of data-intensive applications enabled by advancements in AI, ML and advanced driver-assistance systems (ADAS) [1]. While high-bandwidth memory (HBM) provides an alternative solution, its high cost makes it impractical for many applications. On the other hand, extending the GDDR roadmap beyond GDDR6 through per-pin bandwidth scaling presents significant obstacles: including the reduced link-timing budget and the slow DRAM transistors. This paper introduces an 8Gb DRAM with a single-ended PAM4 interface to redirect and extend the GDDR roadmap. The design supports 22Gb/s/pin in a conventional 1Ynm DRAM process.



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  • Date: 06 May 2021
  • Time: 11:00 AM to 12:30 PM
  • All times are America/Los_Angeles
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  • San Diego, California
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  • Starts 20 April 2021 08:40 AM
  • Ends 05 May 2021 08:40 PM
  • All times are America/Los_Angeles
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  Speakers

Dr. Timothy M. Hollis

Topic:

An 8 Gb GDDR6X DRAM Achieving 22 Gb/s/pin with Single-ended PAM-4 Signaling

Several factors drive the demand for DRAM bandwidth scaling: in addition to established applications in visualization, there has been a proliferation of data-intensive applications enabled by advancements in AI, ML and advanced driver-assistance systems (ADAS) [1]. While high-bandwidth memory (HBM) provides an alternative solution, its high cost makes it impractical for many applications. On the other hand, extending the GDDR roadmap beyond GDDR6 through per-pin bandwidth scaling presents significant obstacles: including the reduced link-timing budget and the slow DRAM transistors. This paper introduces an 8Gb DRAM with a single-ended PAM4 interface to redirect and extend the GDDR roadmap. The design supports 22Gb/s/pin in a conventional 1Ynm DRAM process.

Biography:

Timothy M. Hollis (M’07–SM’13) was born in Palo Alto, CA. He received the B.S. degree in Electrical Engineering from the University of Utah, Salt Lake City, UT in 2003 and the Ph.D. degree in Electrical Engineering from Brigham Young University, Provo, UT in 2007.

He joined the DRAM organization of Micron Technology, Inc., Boise, ID, in 2006 as a circuit designer in the Advanced Architecture group. From 2012-2014 he was a Chipset Architect at Qualcomm, San Diego, CA. He returned to Micron in 2014 where, as a Micron Fellow, he presently leads a Memory Interface Pathfinding team. He has published 17 articles in journals, conference proceedings and technical magazines and holds 163 issued US and international patents.

               Dr. Hollis has served as a member of the IEEE Workshop on Microelectronics and Electron Devices organizing committee from 2010 to the present, including General Chair in 2013. He has served on other IEEE conference committees as well as DesignCon’s technical program committee from 2013-2015. From 2017-2020 he served as the Technology Editor for the IEEE Solid State Circuits magazine and as a guest editor for Memory-related special issues in 2016 and 2019.