Design-Technology Co-Optimization for Reliability and Quality in Advanced Nodes

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Semiconductor demand is rapidly expanding beyond the computing and mobile markets with more products being introduced for automotive, industrial, medical, avionics, and space applications. Chips are increasingly complex with growing functionality through integration of more digital, analog/mixed-signal, and RF sub-systems. Technologies still continue to scale to ever-shrinking dimensions with novel materials and device architectures to realize new power-performance-area levels. Although these new capabilities enable diversified product opportunities, guaranteeing reliability and quality over long product lifetimes has become increasingly challenging in such applications. This paper provides an overview of reliability and product quality challenges in advanced CMOS nodes comprising finFET and fully depleted silicon-on-insulator technologies. Following an overview of intrinsic and extrinsic reliability mechanisms along with design and test methodologies for improving reliability and product quality, it addresses key reliability challenges in fully depleted technologies, such as self-heating, I/O scaling, middle-of-line reliability, dielectric-breakdown monitoring, variation, and stochastic aging. To meet these more stringent requirements in advanced technologies, chip designers and manufacturers must collaboratively optimize chip process technology, design, and test in an even more cohesive and transparent partnership.



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  • Date: 04 Jun 2021
  • Time: 09:00 AM to 10:30 AM
  • All times are America/Los_Angeles
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  • San Diego, California
  • United States

  • Starts 25 May 2021 10:38 AM
  • Ends 04 June 2021 06:38 AM
  • All times are America/Los_Angeles
  • No Admission Charge


  Speakers

Mehul Shroff

Semiconductor demand is rapidly expanding beyond the computing and mobile markets with more products being introduced for automotive, industrial, medical, avionics, and space applications. Chips are increasingly complex with growing functionality through integration of more digital, analog/mixed-signal, and RF sub-systems. Technologies still continue to scale to ever-shrinking dimensions with novel materials and device architectures to realize new power-performance-area levels. Although these new capabilities enable diversified product opportunities, guaranteeing reliability and quality over long product lifetimes has become increasingly challenging in such applications. This paper provides an overview of reliability and product quality challenges in advanced CMOS nodes comprising finFET and fully depleted silicon-on-insulator technologies. Following an overview of intrinsic and extrinsic reliability mechanisms along with design and test methodologies for improving reliability and product quality, it addresses key reliability challenges in fully depleted technologies, such as self-heating, I/O scaling, middle-of-line reliability, dielectric-breakdown monitoring, variation, and stochastic aging. To meet these more stringent requirements in advanced technologies, chip designers and manufacturers must collaboratively optimize chip process technology, design, and test in an even more cohesive and transparent partnership.

Biography:

Mehul Shroff works at NXP Semiconductors in Austin, TX, in the Silicon Reliability group, and is primarily focused on advanced-CMOS and NVM technologies. He has over 25 years of experience in the semiconductor industry. His prior experience includes process integration and device engineering in manufacturing, technology transfer, and development, module development, yield engineering, and test vehicles and test structures. His current interests are focused on reliability tools and methodologies and design for reliability. He holds graduate degrees in Chemical Engineering and Software Engineering.