IEEE CASS-EDS-SSCS & SOEI-HUST Joint Technical Seminar No. 17 “Energy-Efficient Path-Planning Processor for Autonomous Navigation of Micro Robots”

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Recent advances in autonomous micro robots have changed the way humans live and work. Robots are now able to assist humans or even substitute them in many applications. For autonomous navigation, robots need to perceive the environment, make decisions based on the information collected, and autonomously take action. The sensed data are first analyzed to create a map. In the cognition phase, the actions of the robot need to be determined based on its objectives. The tasks include identifying a path, from a given start and endpoint, without colliding with any obstacles. Then motion control commands are executed so as to guide the robots along the safest path. To accelerate path planning, GPUs have been proposed in order to improve the performance. However, GPU-based designs require hundreds of milliseconds to perform path planning and consume a considerable amount of power, which is not feasible for battery-powered micro robots. In this talk, I will present a path planning processor for 2-D/3-D autonomous navigation. Energy and latency are minimized through algorithm-architecture optimization. The chip achieves orders of magnitude improvement in both energy efficiency and latency over the state-of-the-art design.



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  • Start time: 12 Jul 2021 10:30 AM
  • End time: 13 Jul 2021 12:00 AM
  • All times are Asia/Shanghai
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Tencent Meeting (腾讯会议) ID: 917 450 448

  • West No. 1 Building, 1037 Luoyu Road, Wuhan, Hubei, P.R.China, 430074
  • Wuhan
  • China 430074


  Speakers

Chia-Hsiang Yang

Biography:

Prof Yang (M’10-SM’17) received his B.S. and M.S. degrees in Electrical Engineering from the National Taiwan University in 2002 and 2004, respectively. He received his Ph.D. degree from the Department of Electrical Engineering of the University of California, Los Angeles in 2010. He then joined the faculty of the Department of Electronics Engineering at the National Chiao Tung University, Taiwan. In 2015, he moved to the Department of Electrical Engineering at the National Taiwan University, Taiwan, where he is currently a Full Professor. His research interests include energy-efficient integrated circuits and architectures for AI, biomedical, and communication signal processing.

Dr. Yang was a co-recipient of the ISSCC 2013 Distinguished-Technical-Paper Award and ISSCC 2020 Takuo Sugano Award for Outstanding Far-East Paper. In 2018, he was a recipient of the Ta-You Wu Memorial Award from the Ministry of Science and Technology (MOST), Taiwan. He is also the advisor for several student awards, including the 2017 ISSCC Silkroad Award. He serves on the ISSCC and A-SSCC Technical Program Committee and ISSCC SRP Committee. He served as a Guest Editor of the IEEE Journal of Solid-State Circuits (JSSC) and is also serving as an Associate Editor of the IEEE Signal Processing Letters (SPL). He is currently the IEEE CAS Taipei Chapter Chair.