Architecture and Technology Implications of a Chiplet-Based Future
Chiplet architecture is now becoming mainstream, and recognized as fundamental to enabling the continued economically viable growth of power efficient computing. We will cover the benefits of these approaches in enabling lower costs from smaller die combined with modularity to scale performance and configuration, taking examples from industry products. The costs of splitting and modularizing an SOC into chiplets will be discussed, which include the high-bandwidth and low-latency communication requirements between die, overheads of testing and power-managing what used to be individual SOC modules as standalone chips, and engineering the package substrate to provide routing and power delivery resources for the complex integration. Today’s solutions will be evaluated in the context of what will be required from packaging and silicon technologies over the next decade to achieve the true potential of chiplet architecture.
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- Date: 23 Jul 2021
- Time: 08:00 AM to 09:30 AM
- All times are America/Los_Angeles
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- San Diego, California
- United States
- Starts 07 July 2021 09:42 PM
- Ends 22 July 2021 09:42 PM
- All times are America/Los_Angeles
- No Admission Charge
Speakers
Architecture and Technology Implications of a Chiplet-Based Future
Chiplet architecture is now becoming mainstream, and recognized as fundamental to enabling the continued economically viable growth of power efficient computing. We will cover the benefits of these approaches in enabling lower costs from smaller die combined with modularity to scale performance and configuration, taking examples from industry products. The costs of splitting and modularizing an SOC into chiplets will be discussed, which include the high-bandwidth and low-latency communication requirements between die, overheads of testing and power-managing what used to be individual SOC modules as standalone chips, and engineering the package substrate to provide routing and power delivery resources for the complex integration. Today’s solutions will be evaluated in the context of what will be required from packaging and silicon technologies over the next decade to achieve the true potential of chiplet architecture.
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