Architecture and Technology Implications of a Chiplet-Based Future

Share

Chiplet architecture is now becoming mainstream, and recognized as fundamental to enabling the continued economically viable growth of power efficient computing.   We will cover the benefits of these approaches in enabling lower costs from smaller die combined with modularity to scale performance and configuration, taking examples from industry products.  The costs of splitting and modularizing an SOC into chiplets will be discussed, which include the high-bandwidth and low-latency communication requirements between die, overheads of testing and power-managing what used to be individual SOC modules as standalone chips, and engineering the package substrate to provide routing and power delivery resources for the complex integration.  Today’s solutions will be evaluated in the context of what will be required from packaging and silicon technologies over the next decade to achieve the true potential of chiplet architecture.



  Date and Time

  Location

  Hosts

  Registration



  • Date: 23 Jul 2021
  • Time: 08:00 AM to 09:30 AM
  • All times are America/Los_Angeles
  • Add_To_Calendar_icon Add Event to Calendar
If you are not a robot, please complete the ReCAPTCHA to display virtual attendance info.
  • San Diego, California
  • United States

  • Starts 07 July 2021 09:42 PM
  • Ends 22 July 2021 09:42 PM
  • All times are America/Los_Angeles
  • No Admission Charge


  Speakers

Topic:

Architecture and Technology Implications of a Chiplet-Based Future

Chiplet architecture is now becoming mainstream, and recognized as fundamental to enabling the continued economically viable growth of power efficient computing.   We will cover the benefits of these approaches in enabling lower costs from smaller die combined with modularity to scale performance and configuration, taking examples from industry products.  The costs of splitting and modularizing an SOC into chiplets will be discussed, which include the high-bandwidth and low-latency communication requirements between die, overheads of testing and power-managing what used to be individual SOC modules as standalone chips, and engineering the package substrate to provide routing and power delivery resources for the complex integration.  Today’s solutions will be evaluated in the context of what will be required from packaging and silicon technologies over the next decade to achieve the true potential of chiplet architecture.

Biography:

Samuel Naffziger is AMD senior vice president, Corporate Fellow, and Product Technology Architect. Naffziger works across the company to optimize product technology choices and deployment with a continued focus on driving best practice power/performance/area methodology to maximize product competitiveness, efficiency, and cost. Naffziger has been the lead innovator behind many of AMD’s low-power features and chiplet architecture. He has over 32 years of industry experience with a background in microprocessors and circuit design at Hewlett Packard, Intel and AMD. Naffziger received a Bachelor of Science degree in Electrical Engineering from the California Institute of Technology (CalTech) and a Master of Science from Stanford. Naffziger holds more than 130 U.S. patents in the field and authored dozens of publications and presentations on processors, architecture and power management. He is an IEEE Fellow.
 





Agenda

DATE / TIME

Friday, July 23, 2021 @ 8:00-9:15am PDT