Subsampling PLLs for Frequency Synthesis and Phase Modulation

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The tutorial starts with a basic/introductive overview of modern frequency synthesis techniques, delivering basic operation theory in an intuitive fashion. A point of attention is in this context brought to recent subsampling PLL architecture. This architecture overcomes the performance boundaries typically encountered in classical implementations and is redefining today’s state-of-the state of art in frequency synthesis. We will try to explain why. The following part of the tutorial explores the subsampling loop in context of state-of-the art fractional synthesis and phase modulation. We show how to enable fractional-N multiplication modes, while retaining benefits of low-noise subsampling operation. This can be achieved by introducing digital-to-time converter (DTC)-based time domain signal processing. We will discuss potential limitations of this block, and how to overcome them in the analog, or in the digital domain. The versatility of the DTC-based subsampling PLL will further be discussed in context of phase/frequency modulation, which is crucial for accurate polar signaling. We will investigate classical loop-bandwidth limitations and explore how two-point modulation principles can elegantly be applied in context of the explored loop. We will openly discuss potential weak-points of this environment – and how to address them. This talk insists on an intuitive, rather than a strict, mathematical approach to PLLs. It starts from the basic concepts and then gradually expands in complexity, while clearly highlighting the key ideas and pointing to state-of-the-art embodiments.



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  • Date: 10 Dec 2021
  • Time: 08:00 AM to 10:00 AM
  • All times are America/Los_Angeles
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  • Starts 28 November 2021 09:27 PM
  • Ends 09 December 2021 09:27 PM
  • All times are America/Los_Angeles
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Subsampling PLLs for Frequency Synthesis and Phase Modulation

The tutorial starts with a basic/introductive overview of modern frequency synthesis techniques, delivering basic operation theory in an intuitive fashion. A point of attention is in this context brought to recent subsampling PLL architecture. This architecture overcomes the performance boundaries typically encountered in classical implementations and is redefining today’s state-of-the state of art in frequency synthesis. We will try to explain why. The following part of the tutorial explores the subsampling loop in context of state-of-the art fractional synthesis and phase modulation. We show how to enable fractional-N multiplication modes, while retaining benefits of low-noise subsampling operation. This can be achieved by introducing digital-to-time converter (DTC)-based time domain signal processing. We will discuss potential limitations of this block, and how to overcome them in the analog, or in the digital domain. The versatility of the DTC-based subsampling PLL will further be discussed in context of phase/frequency modulation, which is crucial for accurate polar signaling. We will investigate classical loop-bandwidth limitations and explore how two-point modulation principles can elegantly be applied in context of the explored loop. We will openly discuss potential weak-points of this environment – and how to address them. This talk insists on an intuitive, rather than a strict, mathematical approach to PLLs. It starts from the basic concepts and then gradually expands in complexity, while clearly highlighting the key ideas and pointing to state-of-the-art embodiments.

Biography:

Nereo Markulić obtained his Ph.D. degree (2018) summa cum laude from Free University in Brussels, Belgium. His Ph.D. work was in collaboration with imec on Digital Subsampling Phase-Locked Loops and Polar Transmitters. He is currently a research scientist at imec, working on RF and mixed-signal circuits for radar applications and next generation connectivity. He has authored and co-authored publications and patents on PLLs and analog-to-digital converters, a book on frequency synthesis and is a co-recipient of ISSCC 2019 Lewis Winner Award for Outstanding Paper. Dr. Nereo Markulić currently serves on the Technical Program Committee of the IEEE VLSI Circuits symposium.