Si thickness influence on subthreshold currents at high temperatures in FDSOI CMOS

#SOI #High #Temperature

Fully depleted silicon-on-insulator (FDSOI) CMOS with thick buried oxide can operate at higher temperatures compared to bulk CMOS. This work demonstrates, both experimentally and through simulations, that the subthreshold characteristics (off-state leakage current  and subthreshold swing, SS) are improved at high temperatures by reducing the Si thickness  in FDSOI CMOS. Fabricated N and PFET devices exhibits an off-state leakage current less than 300 pA/µm and close to an ideal subthreshold swing of less than 132 mV/dec. at 300 °C. TCAD simulations closely match measured data and show that electrostatic control of the Si layer is key to achieve close to ideal subthreshold swing and low off-state current. With proper gate electrodes FDSOI CMOS can achieve an Ioff < 1nA/µm at 300 °C for both P and NFETs. Ring oscillator simulations, using an UTSOI compact model calibrated to fabricated devices, demonstrate functional behavior at 300 C with 2.2 times increased propagation delay compared to room temperature operation. This result shows that FDSOI CMOS can find use as low power control logic at high temperatures.