Si thickness influence on subthreshold currents at high temperatures in FDSOI CMOS
Fully depleted silicon-on-insulator (FDSOI) CMOS with thick buried oxide can operate at higher temperatures compared to bulk CMOS. This work demonstrates, both experimentally and through simulations, that the subthreshold characteristics (off-state leakage current and subthreshold swing, SS) are improved at high temperatures by reducing the Si thickness in FDSOI CMOS. Fabricated N and PFET devices exhibits an off-state leakage current less than 300 pA/µm and close to an ideal subthreshold swing of less than 132 mV/dec. at 300 °C. TCAD simulations closely match measured data and show that electrostatic control of the Si layer is key to achieve close to ideal subthreshold swing and low off-state current. With proper gate electrodes FDSOI CMOS can achieve an Ioff < 1nA/µm at 300 °C for both P and NFETs. Ring oscillator simulations, using an UTSOI compact model calibrated to fabricated devices, demonstrate functional behavior at 300 C with 2.2 times increased propagation delay compared to room temperature operation. This result shows that FDSOI CMOS can find use as low power control logic at high temperatures.
Date and Time
- Date: 17 Dec 2021
- Time: 03:30 PM to 04:30 PM
- All times are (UTC+01:00) Stockholm
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Assoc. Prof. Per-Erik Hellström of KTH Royal Institute of Technology
High Temperature SOI
Per-Erik Hellström (male) received the M.Sc. and Ph.D. degrees in electrical engineering from KTH Royal Institute of Technology, Stockholm, Sweden, in 1995 and 2000, respectively. His Ph.D. thesis dealt with polycrystalline Si1-xGex as gate material for CMOS technology. Since 2000, he has been at KTH School of Electrical Engineering and Computer Science and was appointed docent in 2006 and Associate Professor in 2021. He acts as manager of KTH’s CMOS process technology and has been instrumental in its establishment. His current research interests include semiconductor process technology, with emphasis on the Si/SiGe/Ge material system, advanced nano-scaled MOSFETs, monolithic 3D integration technology and devices for high temperature and sensing applications. He has published more than 120 papers in refereed journals and conference proceedings.
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