"Nanoscale FinFET Technology for Circuit Designers" Alvin Loke

#Fin-Fet #Circuits #Design #CMOS

Abstract: Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-channel control that achieves digital power reduction while increasing device performance for a given area. As system-on-chip technology remains driven by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must continue to adapt to new technology constraints. We attempt to summarize the challenges and technology considerations encountered when we port analog/mixed-signal designs to a finFET node. At 16/14 nm and beyond, designers also face many implications from scaling innovations leading to the finFET such as mechanical stressors, high-K gate dielectric and metal gate, multiple and spacer-based patterning, and a very complex middle-end-of-line.