Towards Energy-Efficient Domain-Specific In-Sensor and In-Memory Accelerators, From Device to Algorithm

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Internet of Things (IoT) devices are projected to attain an $1100B market by 2025, with a web of interconnection projected to comprise approximately 75+ billion IoT devices. The large number of IoTs consist of sensory systems that enable massive data collection from the environment and people. However, considerable portions of the captured sensory data are redundant and unstructured. Data conversion of such large raw data, storing in volatile memories, transmission, and computation in on-/off-chip processors, impose high energy consumption, latency, and a memory bottleneck at the edge. Moreover, because renewing batteries for IoT devices is very costly and sometimes impracticable, energy harvesting devices with ambient energy sources and low maintenance have impacted a wide range of IoT applications such as wearable devices, smart cities, and the intelligent industry. Therefore, high-speed, low-power and normally-off computing domain-specific architectures should be explored and developed to overcome these issues. Motivated by the aforementioned concerns, in this talk, I will be focusing on cross-layer (device/circuit/architecture/application) co-design of energy-efficient and high-performance processing- in-sensor and processing- in-memory platforms for implementing complex AI and machine learning tasks, bioinformatics tasks, graph processing, etc. I explain how to leverage innovations from both device to architecture to integrate sensor, memory, and logic to break the existing memory and power walls.



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  • Date: 10 Mar 2022
  • Time: 05:50 PM to 07:44 PM
  • All times are (UTC-05:00) Eastern Time (US & Canada)
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  • 154 Summit Street, Newark, NJ 07102
  • NJIT
  • Newark, New Jersey
  • United States 07102
  • Building: ECEC
  • Room Number: 202
  • Click here for Map

  • Dr. Ajay K. Poddar, Email:akpoddar@ieee.org

    Dr. Edip Niver, email: edip.niver@njit.edu

    Dr. Durga Misra,  Email: dmisra@ieee.org

    Dr. Anisha M. Apte, Email: anisha_apte@ieee.org

     

  • Co-sponsored by IEEE North Jersey Section
  • Starts 02 February 2022 12:49 PM
  • Ends 10 March 2022 04:49 PM
  • All times are (UTC-05:00) Eastern Time (US & Canada)
  • No Admission Charge


  Speakers

Prof. Shaahin Angizi Prof. Shaahin Angizi of New Jersey Institute of Technology

Topic:

Towards Energy-Efficient Domain-Specific In-Sensor and In-Memory Accelerators, From Device to Algorithm

Internet of Things (IoT) devices are projected to attain an $1100B market by 2025, with a web of interconnection projected to comprise approximately 75+ billion IoT devices. The large number of IoTs consist of sensory systems that enable massive data collection from the environment and people. However, considerable portions of the captured sensory data are redundant and unstructured. Data conversion of such large raw data, storing in volatile memories, transmission, and computation in on-/off-chip processors, impose high energy consumption, latency, and a memory bottleneck at the edge. Moreover, because renewing batteries for IoT devices is very costly and sometimes impracticable, energy harvesting devices with ambient energy sources and low maintenance have impacted a wide range of IoT applications such as wearable devices, smart cities, and the intelligent industry. Therefore, high-speed, low-power and normally-off computing domain-specific architectures should be explored and developed to overcome these issues. Motivated by the aforementioned concerns, in this talk, I will be focusing on cross-layer (device/circuit/architecture/application) co-design of energy-efficient and high-performance processing- in-sensor and processing- in-memory platforms for implementing complex AI and machine learning tasks, bioinformatics tasks, graph processing, etc. I explain how to leverage innovations from both device to architecture to integrate sensor, memory, and logic to break the existing memory and power walls.

Biography:

Shaahin Angizi is an Assistant Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology (NJIT), and the director of the Advanced Circuit-to-Architecture Design Laboratory (ACAD Lab). He received his Ph.D. in Electrical Engineering at the School of Electrical, Computer and Energy Engineering, Arizona State University (ASU). His research interests include the cross-layer design of energy-efficient and high-performance processing-in-memory, processing-in-sensor, and ASIC platforms to enhance complex machine learning tasks, bioinformatics, and graph processing. He has authored and co-authored 70+ research articles in top-ranked international journals and top-tier electronic design automation conferences such as IEEE TNANO, IEEE TCAD, IEEE TC, IEEE TCASI, IEEE TETC, DAC, DATE, ICCAD, ASP-DAC, etc. He received the “Best Ph.D. research award - 1st place” at the Design Automation Conference’s Ph.D. forum in 2018, two “Best Paper” awards at the IEEE Computer Society Annual Symposium on Very Large-Scale Integration (VLSI) in 2017 and 2018, and a “Best Paper” award at the ACM Great Lakes Symposium on VLSI in 2019. He has served as a technical reviewer for over 30 international journals/conferences, such as IEEE TC, TVLSI, TCAD, TNANO, TCAS, ESL, ACM JETC, MICRO, DAC, ASP-DAC, DATE, ICCAD, ICCD, GLSVLSI, ISVLSI, etc.
For more information, please see http://shaahinangizi.com.

Email:

Address:ECE Dept, NJIT, 161 Warren Street, Newark, New Jersey, United States, 07102





Agenda

Event Time: 6:00PM to 7:30 PM

Venue: Kiernan Conference Room (ECE 202),  ECEC, NJIT, Newark

Talk by Prof. Shaahin Angizi

Seminar in ECE 202 All Welcome: There is no fee/charge for attending IEEE technical seminar. You don't have to be an IEEE Member to attend. Refreshment is free for all attendees. Please invite your friends and colleagues to take advantage of this Invited Lecture.