SerDes Architecture from Impairments (On-Site)

#SerDes #High-Speed #Communications #Wireline #IC #ASIC #Microeletronics
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Abstract– Over the past three decades, the demand of communication makes different kinds of standards evolute exponentially in speed. Along with the higher and higher wireline data rates, more impairments in the SerDes system and circuitry may reasonably change the link architecture in an evolution. For example, the impairments, such as an inter-symbol interference, ISI (due to frequency dependent attenuation), crosstalk, reflection, noise, jitter, linearity, device mismatch, capacitive or inductive parasitic, power/ground integrity, etc., could not be a concern at old generation SerDes, but could be an issue at a high-speed SerDes system and requires a different architecture to mitigate the impairments. 
This presentation will begin with providing an introduction of a wireline serial link, including a few impairments. Then move forward with rearchitecting the SerDes topology to mitigate those impairments. The corresponding SerDes system and circuit design techniques would be explored during the iterations between those impairments and rearchitecting process. Finally, the generic high-speed Serdes architecture with some circuit images will be reviewed and discussed. A further Q&A discussion will be performed in the end of this presentation as well. 



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  • Date: 12 May 2022
  • Time: 09:30 AM to 12:30 PM
  • All times are (UTC+01:00) Warsaw
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  • AGH University of Science and Technology
  • Av. Mickiewicza 30
  • Kraków, Malopolskie
  • Poland 30-059
  • Building: B1
  • Room Number: 121
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  • Co-sponsored by Silicon Creations Poland


  Speakers

Chung-Chun Chen (CC) Chung-Chun Chen (CC) of Silicon Creations LLC

Topic:

SerDes Architecture from Impairments

Abstract Over the past three decades, the demand of communication makes different kinds of standards evolute exponentially in speed. Along with the higher and higher wireline data rates, more impairments in the SerDes system and circuitry may reasonably change the link architecture in an evolution. For example, the impairments, such as an inter-symbol interference, ISI (due to frequency dependent attenuation), crosstalk, reflection, noise, jitter, linearity, device mismatch, capacitive or inductive parasitic, power/ground integrity, etc., could not be a concern at old generation SerDes, but could be an issue at a high-speed SerDes system and requires a different architecture to mitigate the impairments. 
This presentation will begin with providing an introduction of a wireline serial link, including a few impairments. Then move forward with rearchitecting the SerDes topology to mitigate those impairments. The corresponding SerDes system and circuit design techniques would be explored during the iterations between those impairments and rearchitecting process. Finally, the generic high-speed Serdes architecture with some circuit images will be reviewed and discussed. A further Q&A discussion will be performed in the end of this presentation as well. 

Biography:

Chung-Chun (CC) Chen is a Director of Analog/Mixed-Signal Design, since 2019. During 2018 – 2019, CC joined Ubilinx Technology (Realtek Semiconductor Group) in San Jose, CA, and he was the driver/architect of Realtek’s high-speed Serdes technologies. During 2011 – 2018, CC was a senior analog designer/manager at Silicon Creations, while he designed analog IP products including Ring-based & LC tank PLLs, Serializer, De-serializer with all clocking building blocks (PLL/CDR, phase interpolator) and equalization (FFE, CTLE, DFE) circuitry. Before, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta. Earlier, he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support. 
CC (S’02–M’09–SM’17) was born in Taipei, Taiwan, in 1979. He received the M.S. and Ph.D. degrees in EE from National Taiwan University, Taipei, Taiwan, in 2004 and 2009, respectively. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.

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