A Phasor Measurement Unit (PMU) Algorithm for FPGA implementation

#Frequency #Measurement #FPGA #Phasor

Dear IEEE members and guests,

The next IEEE Control, Aerospace and Electronic Systems (CAES) seminar will be on Monday, 27^th June, 2022 at 7:30 pm (Adelaide time).

The speaker is Dr C. J. Kikkert BE (Hons I), PhD, FIEAust, LSMIEEE, CPEng, he will be presenting a seminar on:

A Phasor Measurement Unit (PMU) Algorithm for FPGA implementation 

Please aim to join the WebEx meeting beforehand, so we can start on time.

https://ieeemeetings.webex.com/ieeemeetings/j.php?MTID=m7aa7e54b1fe8edc8186f7a04920ed965

Webinar number (access code): 2538 375 4438

Also, please check out the IEEE SA Section website: https://r10.ieee.org/saus/

Regards

Waddah Al-Ashwal

IEEE SA CAES Chapter Chair

A Phasor Measurement Unit (PMU) Algorithm for FPGA implementation 

Phasor Measurement Units are used to measure Voltage, Phase, Frequency and Rate of Change of Frequency. A Voltage Phasor accuracy better the 1% and frequency error of less than 5mHz (0.01%) and must be obtained within 2 mains cycles time. To ensure high measurement availability and reliability, an FPGA implementation of the PMU is being implemented. The seminar will describe the PMU algorithm, which includes IQ demodulation, phasor conversion and filtering of the mains waveform. The seminar will discuss the Digital Signal Processes (DSP) choices required to ensure a minimum time delay FPGA implementation, whilst achieving the required measurement accuracy.