#PLL #Frequency #Synthesis #Jitter

Abstract: What is a good frequency synthesizer? A survey of CMOS phase-locked loops (PLLs) over the last two decades shows that the overall performance of PLL-based frequency synthesizers is bounded by a tradeoff between noise, area, and power consumption. Analog PLLs with a charge-pump integrator (Type-II) suffer from charge-pump and detector noise, and are area- and power-hungry. All-digital PLLs are compact and friendly to technology scaling but limited in noise performance under a restrained power budget.

The simplest frequency synthesizer is one utilizing the least noise-inducing components in the loop. The recipe to design the lowest noise synthesizer is simple: (1) Choose the VCO with the lowest phase noise. (2) Reduce its low-offset phase noise by locking it to the cleanest frequency reference with a large loop bandwidth. (3) Eliminate/suppress other noise sources. Such a loop can be realized as Type-I, without an integrator in the loop filter. Such synthesizers thus comprise subsampling Type-I PLLs and injection-locked (Type-I) PLLs. They achieve low noise performance in a compact footprint and low power budget. And the limitations of classical Type-I, subsampling, and injection-locked topologies can be remedied using two classical design philosophies - 1) a simple design is often a good design, and 2) use digital CMOS where it is good at. Such digitally-assisted analog synthesizers include the best of both worlds.