Optimization of DSP-Based Optical Communication Links Beyond 100Gbps

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Progress in computation and communication is increasingly bottlenecked by integrated circuit I/O. Previously reserved for communication over 100’s of kilometres, today optical links are widely viewed as the primary solution for chip-to-chip links above 100 Gbps and up to 1 km.  Meanwhile, CMOS technology scaling has led us toward integrated circuit transceivers that are, essentially, complete modems: thin but critical analog front-end circuits and a large custom DSP.  This presentation will describe how to co-design of DSP transceivers with a thin but critical analog front-end and the associated optical components to create optical links serving future datacentre communication needs.  As an example, a 4-PAM CMOS linear TIA designed in a FinFET technology consuming less than 50 mW and co-packaged alongside photodiodes is presented. The circuits and packaging are co-designed to maximize the passive front-end BW. Experimental results confirm the integrated optical fibre receiver operates up to 160-Gb/s using a single wavelength with a suitable DSP.



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  • Date: 09 Aug 2022
  • Time: 02:00 PM to 03:30 PM
  • All times are (UTC-05:00) Eastern Time (US & Canada)
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  • 1515 Ste-Catherine West
  • Montreal, Quebec
  • Canada H3G1M8
  • Building: EV
  • Room Number: 1.162



  Speakers

Dr. Tony Chan Carusone Dr. Tony Chan Carusone of Alphawave/University of Toronto

Topic:

Optimization of DSP-Based Optical Communication Links Beyond 100Gbps

Biography:

Tony Chan Carusone has been a faculty member at the University of Toronto since completing his Ph.D. there in 2002.  He has co-authored eight award-winning papers on chip-to-chip and optical communication circuits, ADCs, and clock generation.  He has also been a consultant to industry since 1997.  He is currently the Chief Technology Officer of Alphawave in Toronto, Canada.

Dr. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and served on the Technical Program Committee of the International Solid-State Circuits Conference from 2015-2021.  He co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He has served as Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs, an Associate Editor for the IEEE Journal of Solid-State Circuits, and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters.  He is a Fellow of the IEEE.

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