Recent Advances and Trends in Advanced Packaging

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In this lecture, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. The UCIe (Universal Chiplet Interconnect Express) will also be briefly mentioned. Different substrates, such as size, pin-count, and metal linewidth and spacing for heterogeneous integration packaging, are examined. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.



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  • Date: 25 Aug 2022
  • Time: 05:00 PM to 07:00 PM
  • All times are (UTC-08:00) Pacific Time (US & Canada)
  • Add_To_Calendar_icon Add Event to Calendar
  • AZ Auditorium
  • 10155 Pacific Heights Blvd
  • San Diego, California
  • United States 92121

  • Starts 12 August 2022 11:00 AM
  • Ends 25 August 2022 05:00 PM
  • All times are (UTC-08:00) Pacific Time (US & Canada)
  • No Admission Charge


  Speakers

Dr. John Lau Dr. John Lau of Unimicron Technology Corporation

Topic:

Recent Advances and Trends in Advanced Packaging

In this lecture, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. The UCIe (Universal Chiplet Interconnect Express) will also be briefly mentioned. Different substrates, such as size, pin-count, and metal linewidth and spacing for heterogeneous integration packaging, are examined. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

Biography:

John, with more than 40 years of research and development, and manufacturing experiences in semiconductor packaging and surface-mount technology assembly, has published more than 510 peer-reviewed papers, 40 issued and pending U.S. patents, and 22 textbooks. John is an elected ASME Fellow, IEEE Fellow, and IMAPS Fellow, and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.