IEEE CASS Distinguished Lecture titled 'In-Memory Computing Circuits Using Multi Level Spin Memories'

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Conventional CMOS technology has reached the brink of its scaling limits and poses significant challenges for the development of next generation high-speed, low-power, cost-effective memory, and processing devices. In the post-CMOS era, “Spintronics” could emerge as a potentially viable interdisciplinary field with credible technological perspectives. This technology exploits an electron’s spin orientation and its associated magnetic moment as a state variable instead of a conventionally used charge in CMOS technology. In general, spintronic devices are layered structures of magnetic materials that provide the non-volatile storage options and manipulations of logic states. Spin transfer torque (STT) and spin orbit torque (SOT) devices using magnetic tunnel junctions (MTJs) have become strong contenders for the non-volatile embedded memory architectures with the capability of implementing the concepts of "logic-in-memory" and "material-device-circuit co-design". The spin torque devices offer the features of "universal memory", i.e. high-speed, nonvolatility, high density, and low-power, high-endurance and CMOS process compatibility. The memory density is in ever increasing demand due to complex functionalities and storage requirements. This talk presents the operation principle and performance comparison of spintronics based single-bit STT and SOT magnetic RAM (MRAM), dual-level cells (DLCs), three-level cells (TLCs), and four-level cells (FLCs). It is observed that the multilevel MRAM technology is far more efficient in terms of static power consumption and area overhead, respectively as compared to the available SRAMs. This talk will also discuss in-memory computing circuits using multi-level cells.



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  • Date: 15 Nov 2022
  • Time: 02:00 PM to 03:30 PM
  • All times are (UTC+01:00) Copenhagen
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Virtual link will be shared with participants.



  Speakers

Brajesh Kumar Kaushik Brajesh Kumar Kaushik of Indian Institute of Technology Roorkee, India

Topic:

In-Memory Computing Circuits Using Multi Level Spin Memories

Conventional CMOS technology has reached the brink of its scaling limits and poses significant challenges for the development of next generation high-speed, low-power, cost-effective memory, and processing devices. In the post-CMOS era, “Spintronics” could emerge as a potentially viable interdisciplinary field with credible technological perspectives. This technology exploits an electron’s spin orientation and its associated magnetic moment as a state variable instead of a conventionally used charge in CMOS technology. In general, spintronic devices are layered structures of magnetic materials that provide the non-volatile storage options and manipulations of logic states. Spin transfer torque (STT) and spin orbit torque (SOT) devices using magnetic tunnel junctions (MTJs) have become strong contenders for the non-volatile embedded memory architectures with the capability of implementing the concepts of "logic-in-memory" and "material-device-circuit co-design". The spin torque devices offer the features of "universal memory", i.e. high-speed, nonvolatility, high density, and low-power, high-endurance and CMOS process compatibility. The memory density is in ever increasing demand due to complex functionalities and storage requirements. This talk presents the operation principle and performance comparison of spintronics based single-bit STT and SOT magnetic RAM (MRAM), dual-level cells (DLCs), three-level cells (TLCs), and four-level cells (FLCs). It is observed that the multilevel MRAM technology is far more efficient in terms of static power consumption and area overhead, respectively as compared to the available SRAMs. This talk will also discuss in-memory computing circuits using multi-level cells.

Biography:

Brajesh Kumar Kaushik 

received Doctorate of Philosophy (Ph.D.) in 2007 from Indian Institute of Technology, Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, as Assistant Professor in December 2009; promoted to Associate Professor in April 2014; and since Aug 2020 he has been serving as full Professor. He had been Visiting Professor at TU-Dortmund, Germany in 2017; McGill University, Canada in 2018 and Liaocheng University, China in 2018. He is currently serving as Visiting Lecturer of SPIE society to deliver lectures in the area of Spintronics and Optics at SPIE chapters located across the world. He regularly serves as General Chair, Technical Chair, and Keynote Speaker of reputed international and national conferences. He also served as Chairman and Vice Chairman of IEEE Roorkee sub-section. Dr. Kaushik is a Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. He is currently serving as Distinguished Lecturer (DL) of IEEE Electron Devices Society (EDS) to offer EDS Chapters with quality lectures in his research domain. He is Editor-in-Chief of Elsevier Journal, Memories-Materials, Devices, Circuits and Systems; an Editor of IEEE Transactions on Electron Devices; Associate Editor of IEEE Sensors Journal; Associate Editor of IET Circuits, Devices & Systems; Editor of Microelectronics Journal, Elsevier; Editorial Board member of Journal of Engineering, Design and Technology, Emerald and Circuit World, Emerald. He is among top 2% scientists in world as per Stanford University report of 2019. He is currently serving as member of two technical committees namely, Spintronics (TC-5), and Quantum Computing, Neuromorphic Computing and Unconventional Computing (TC-16) of IEEE Nanotechnology Council. He is also Regional coordinator (R10) of IEEE Nanotechnology Council Chapters. He has 12 books to his credit published by reputed publishers such as CRC Press, Springer, Artech and Elsevier. One his books, titled “Nanoscale Devices: Physics, Modeling, and Their Application”, CRC Press won 2018 Outstanding Book and Digital Product Awards in the Reference/Monograph Category from Taylor and Francis Group. He has been offered with fellowships and awards from DAAD, Shastri Indo Canadian Institute (SICI), ASEM Duo, United States-India Educational Foundation (Fulbright-Nehru Academic and Professional Excellence). His research interests are in the areas of high-speed interconnects, carbon nanotube-based designs, organic electronics, device circuit co-design, optics & photonics-based devices, image processing, spintronics-based devices, circuits and computing.

Email:

Address:Deptt.of Electronics and Communication Engineering, Indian Institute of Technology-Roorkee, Roorkee, Uttaranchal, India, 247667