Recent Trends and Advances in High Performance Fractional-N PLL Design
High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, fast locking, and low power operation. Both circuits design and digital calibration techniques will be presented in detail. In addition, recent advances in reference clock generation will also be discussed as it is crucial for high performance PLLs.
Date and Time
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- Date: 18 Nov 2022
- Time: 10:00 AM to 11:00 AM
- All times are (UTC-07:00) Mountain Time (US & Canada)
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- Unniversity of Calgary
- Calgary, Alberta
- Canada T2N1N4
- Building: ICT
- Room Number: 516
- Contact Event Host
- Co-sponsored by Solid-State Circuits
- Starts 29 September 2022 10:00 AM
- Ends 18 November 2022 09:00 AM
- All times are (UTC-07:00) Mountain Time (US & Canada)
- No Admission Charge
Speakers
Wanghua Wu of Samsung Semiconductor Inc
Recent Trends and Advances in High Performance Fractional-N PLL Design
High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, fast locking, and low power operation. Both circuits design and digital calibration techniques will be presented in detail. In addition, recent advances in reference clock generation will also be discussed as it is crucial for high performance PLLs.
Biography:
Wanghua Wu (M’07) received the B.Sc. degree (with honors) from Fudan University, Shanghai, China, in 2004, M.Sc. degree (cum laude) and Ph.D. degree from Delft University of Technology, The Netherlands in 2007 and 2013, respectively, all in electrical engineering.
From 2013 to 2016, she was an RFIC Design Engineer in Marvell, developing high-performance frequency synthesizers for WLAN transceivers. Since 2016, she has been with Samsung Semiconductor Inc. USA. She is currently a Senior Manager and Principal Engineer, focusing on advanced cellular RFIC design. Her research interest is on CMOS frequency synthesis for wireless applications.
She is currently served as the Technical Program Committee member of IEEE International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC), and Radio Frequency Integrated Circuits Symposium (RFIC).
Address:United States