Swiss IEEE EPS and SSCS Lecture- Chiplet Design and Heterogeneous Integration Packaging
Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.
- System-on-Chip (SoC)
- Why Chiplet Design?
- Chiplet Design and Heterogeneous Integration Packaging
- Chip partition and Heterogeneous Integration
- Chip split and Heterogeneous Integration
- Advantages and Disadvantages
- Lateral Communication between Chiplets (e.g., Bridges)
- Bridge Embedded in Build-up Package Substrate
- Bridge Embedded in Fan-Out EMC with RDLs
- UCIe
- Hybrid Bonding Bridge
- Chiplet Design and Heterogeneous Integration Packaging - Multiple System and Heterogeneous Integration
- Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration)
- Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration)
- Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration)
- Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration)
- Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration)
- Summary
- Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging
Date and Time
Location
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Registration
- Date: 20 Apr 2023
- Time: 03:30 PM to 06:00 PM
- All times are (UTC+02:00) Bern
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- ETH Zurich
- Gloriastrasse 35
- Zurich, Switzerland
- Switzerland
- Room Number: E-81
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- Co-sponsored by ETH Zurich
- Starts 16 February 2023 08:30 PM
- Ends 19 April 2023 08:30 PM
- All times are (UTC+02:00) Bern
- 0 in-person spaces left!
- No Admission Charge
Speakers
John H Lau of Unimicron Technology Corporation
Chiplet Design and Heterogenous Integration Packaging
Biography:
John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging has published more than 518 peer-reviewed papers (377 are the principal investigator), 42 issued and pending US patents (27 are the principal inventor), and 23 textbooks (all are the first author) on, e.g., Chiplet Design and Heterogeneous Integration Packaging (Springer, 2023). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow, and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.
Agenda
15:30 -15:45 - Welcome and Introduction, - Chairman IEEE EPS and SSCS chapters Switzerland
15:45 -17:00 - Lecture on "Chiplet Design and Heterogenous Integration Packaging" by Dr. John H Lau Unimicron Technology Corporation
17:00 -18:00- Apero