Fernando Jose da Costa of FEI University

The crescent demand for performance and speed of the integrated circuits has led the semiconductor industry to focus on the ever-increasing number of integrated devices in the same chip. Since the middle of the 60s’, this number has followed the Moore´s Law, which states that the number of integrated devices should double every two years. With the process of continuous dimensions reduction of the devices, degraded behavior arose due to a harmful effect called short channel effects, and also, silicon has reached its limits with respect to the devices’ shrinkage. To keep the continuous development, not only Moore´s law is observed to maintain the increase in devices’ integration in recent technologies, but also new interconnect and packaging schemes and new compact layout rules techniques have also become an interest in the research to maintain the development to supply the system´s demand.

During the lecture, the characteristics of the coupling effects that can arise with the reduction of the distance between the devices will be outlined, aiming at an optimization of the space in the silicon wafer with a compact layout scheme.

Biography:

Fernando Jose da Costa obtained the Master’s Degree, in Electrical Engineering, from in 2018. He is an IEEE student member and a PhD student in Electrical Engineering at Centro Universitario FEI under the sponsorship of the Brazilian Federal Foundation for Support and Evaluation of Graduate Education – CAPES. Currently he is staying a time as an invited visiting scholar at the New Jersey Institute of Technology–NJIT. He has participated in international conferences such as Sb Micro, EUROSOI ULIS, LASCAS and LAEDC. His current interests are focused on SOI CMOS technology, more specifically on electrical and thermal characterization of MOSFET's transistors.

Email:

Address:Department of Electrical EngineeringThe University Center of FEI, , São Bernardo do Campo, Sao Paulo, Brazil