VLSI Design using Cadence EDA tools

#electronics

A 5 day Faculty development programme on “VLSI Design using Cadence EDA tools” was organized by Department of Electronics and Communication in association with IEEE student branch, Department ECE, Nitte Meenakshi Institute of Technology from 23^rd  to 28^th January 2023.

The inaugural event held on 23^rd  January was presided over by                                          Dr. Ramachandra A C, Professor & Head, Department of Electronics & Communication Engineering,  Nitte Meenakshi Institute of Technology, Bangalore,

gave a Brief talk on a journey from Knowledge to skill. It gave the participants ample number of tips to bridge the skill gaps between the academia and the industry.

           The  Session started with Introduction to cadence tool by Dr.Sowmya Madhavan ,  Dr.Naveen I G and Pradeep Kumar S which gave an insight on Analog and Mixed Signal IC Design Flow, followed by an informative talk on CMOS Process Technology, Design and analysis of Analog circuit and its importance. Also gave hands on Basics of different tools available in VLSI, invoking the tools Creating symbol and test bench for the inverter.

On Day 2, Hands on Sessions By Entuple Technologies - Mr. Shivaprasad, Application Engineer, Entuple Technologies was the resource person. The session begins with designing Inverter at schematic level , Inverter Test Circuit and different circuit level calculations like power dissipation ,Delay and Area calculations were shown to participants to implement the IC design flows.

The afternoon session started by briefing about Schematic design and Mapping of schematic to Layout generation. Layout Level was verified with respect to Schematic in terms of Design Rule Check (DRC) , Layout versus Schematic (LVS) and Parasitic Extraction.

Day 3 of training on  Cadence started with discussion on doubts in layout. Demonstrated the Front end design with 8 bit counter example.  Initially, the counter code was developed in Verilog and the test bench was written. Then NC launch tool was used to run the simulation. Post simulation, synthesis was done to obtain the netlist.

        During the afternoon session, all steps of Physical Design were demonstrated. Floorplanning, Powerplanning, Placement, Clock Tree Synthesis, Routing and Timing analysis were performed on the same RTL design. Finally, generation of GDSII file also was shown.

The Day 4 continued with the Back annotation and had a brief interaction on Full Custom IC Design and Semi Custom IC Design. Given Insight of working with the FinFET Design. Also hands on was given on Design of analog circuit using FinFET technology.

The Day 5 started with the how to implement the projects with the Cadence tool also different problem statements were  discussed and finally concluded with discussion on Carrier Opportunities in VLSI Industry.

Faculty development programme was attended by 12  participants.

The Event was successfully coordinated by the Dr.Sowmya Madhavan.

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• Nitte Meenakshi Institute of Technology
• Bengaluru, Karnataka
• India 560064

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• Starts 26 December 2022 04:01 AM UTC
• Ends 20 January 2023 04:01 PM UTC
• No Admission Charge

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