Yiran Chen of Duke University

Artificial Intelligence (AI) has become pervasive in cloud and edge systems alike. However, despite the time-sensitive nature of many edge AI tasks, such edge systems are resource constrained, making the deployment of many large AI models on the edge unfeasible. Cross-layer optimizations bridge the gap between model size and edge resources by (1) reducing the computation and memory cost of the model and (2) improving the performance and efficiency of the device. In this talk, we present an overview of our effort in boosting the deployment of AI in edge systems. We first introduce efficient AI models via hardware-friendly model compression and topology-aware Neural Architecture Search to optimize quality-efficiency trade-off on AI models. Then, we involve cross-optimized design of edge AI hardware using efficient dataflows, sparse-skipping mechanisms, and quantization. Lastly, we demonstrate the capabilities of such AI models on a wide range of applications and scenarios, such as Electronic Design Automation (EDA) and reliable Machine Learning. Through the previous exploration, we present our vision on the future challenges and opportunities of full-stack Edge AI.

Biography:

Yiran Chen received B.S (1998) and M.S. (2001) from Tsinghua University and Ph.D. (2005) from Purdue University. After five years in the industry, he joined the University of Pittsburgh in 2010 as Assistant Professor and was promoted to Associate Professor with tenure in 2014, holding Bicentennial Alumni Faculty Fellow. He is now the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University and serving as the director of the NSF AI Institute for Edge Computing Leveraging the Next-generation Networks (Athena), the NSF Industry-University Cooperative Research Center (IUCRC) for Alternative Sustainable and Intelligent Computing (ASIC), and the co-director of Duke Center for Computational Evolutionary Intelligence (DCEI). His group focuses on the research of new memory and storage systems, machine learning and neuromorphic computing, and mobile computing systems. Dr. Chen has published 1 book and more than 500 technical publications and has been granted 96 US patents. He has served as the associate editor of more than a dozen international academic periodicals and served on the technical and organization committees of more than 60 international conferences. He is now serving as the Editor-in-Chief of the IEEE Circuits and Systems Magazine. He received 9 best paper awards, 1 best poster award, and 15 best paper nominations from reputable international conferences and workshops. He received numerous awards for his technical contributions and professional services such as the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, etc. He has been the distinguished lecturer of IEEE CEDA and CAS. He is a Fellow of the ACM, IEEE, and AAAS, and now serves as the chair of ACM SIGDA.

Email:

Address:405 Wilkison Building, 534 Research Dr., , Durham, North Carolina, United States, 27705