Alvin Loke of NXP Semiconductors

CMOS scaling maintains economic relevance with 5nm SoCs already in high-volume production for 2.5 years and 3nm well into risk production. Modest feature size reduction and design/technology innovations co-optimized primarily for logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we start with a brief history of transistor evolution to motivate the migration from planar Dennard-era transistors to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges impacting design. To address the growing effort required for physical design closure, we cover design strategies including density-friendly layout, continuous active area layout, and template-based analog cells. We conclude with a discussion of what remains in finFET development and a peek at transistor architectures on the horizon.

Biography:

Alvin Loke is a Fellow at NXP Semiconductors in San Diego, having previously worked at Agilent, AMD, Qualcomm, and TSMC. He has extensive technology and analog design experience on CMOS nodes spanning 250nm to 2nm. He received his BASc in engineering physics from UBC, and MS and PhD from Stanford. Upon graduating, he spent several years in CMOS process integration. Since 2001, he has worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom member and Webinar Chair, CICC Committee Member, Denver and San Diego Chapter Chair, as well as JSSC and SSCL Guest Editor. He currently serves in the VLSI Symposium committee as well as SSCS Chapters Chair and Solid-State Circuits Magazine Guest Editor. Alvin has authored dozens of invited publications including the CICC 2018 Best Paper; short courses at ISSCC, VLSI Symposium, and BCICTS; and keynote at ICICDT. He holds 29 US patents.

Email:

Address:San Diego, United States