Validation and Risk Assessment Method for System-in-Package Design

#reliability #SIP #Risk #assessment
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System-in-Package (SiP) technology provides a great opportunity for consumer electronics companies to make products with smaller form factor, more functions, and better reliability performance. One key reason for SiP’s success is the encapsulated structure using molding compound, which can provide protection to all the components inside and allows reduced component-to-component spacing. However, if the design or the manufacturing process have flaws, failures can also happen inside of SiP, and engineers have to spend much more efforts and time to conduct fault isolation, understand the root cause, and make related corrective actions. In this regard, risks are borne not only by the SiP manufacturers, but also the system integrators and Original Equipment Manufacturers (OEMs) who needs to assemble SiP into the final product. Therefore, a comprehensive design and manufacturing assessment plan and an effective validation method at an early stage of the SiP development will be extremely critical so that the risk can be identified in advance, and the impact to the product launch can be minimized. This paper focuses on two types of encapsulant related failures, molding void and component internal delamination. By presenting several cases that are encountered during SiP development, their failure mechanisms are studied, and the methodology to detect the failure and assess the risk are also discussed.



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  • Date: 08 May 2023
  • Time: 06:00 PM to 08:00 PM
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  • 201S. Rengstorff Avenue
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  • Starts 03 May 2023 07:26 PM
  • Ends 08 May 2023 08:00 PM
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Dr Yuan Zhang

Biography:

Speaker: Yuan Zhang Ph.D. Principal Engineer, Amazon Lab126. yzhangm@amazon.com

Bio:

Dr. Zhang is Principal Engineer at Amazon Lab126 and focuses on semiconductor reliability with 13+ years of experience in semiconductor packaging and reliability engineering. She works with cross functional teams and semiconductor suppliers to develop the leading-edge semiconductor components for multiple Amazon products. Before joining Amazon, she worked at Intel as technical leader for SoC package design and connectivity product reliability. Dr. Zhang is an active contributor to connect academia and industry. Since 2017 she has served as conference section chair, paper reviewer, and student mentor for ASME and IEEE conferences