CC Chen - Challenges of Overcoming the SERDES Receiver’s Stressed Eye Test among Protocols
Over the past three decades, the demand for wireline communication makes different kinds of standards evolute exponentially in speed. Also, to accommodate different link partners in the ecosystem, the receiver must tolerate different signal qualities at the inputs; therefore, most protocols specify the worst-case input signal to make sure the target receiver can still operate well such that it can perform better than the stressed eye under any better link conditions. For example, the added impairments of the stressed-eye test could be inter-symbol interference (ISI), broadband noise, random jitter, sinusoidal jitter (SJ), differential mode sinusoidal interference (DMSI), common mode sinusoidal interference (CMSI), etc. at the input.
This presentation will begin with introducing the industry trends of a wireline serial link. Then move forward with a multi-protocol (MP) SerDes introduction. We’ll then show comprehensive impairments of the receiver’s stressed eye test from different protocols, and the corresponding design optimizations for improving the stressed-eye tolerance will also be discussed. A further Q&A discussion will be covered at the end of this presentation.
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- AGH University
- Kraków, Malopolskie
- Poland 30-059
- Building: B-1
- Room Number: 121
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- Co-sponsored by Silicon Creations
Speakers
Chung-Chun (CC) Chen
Biography:
CC has been with Silicon Creations since 2011 and is a principal circuit architect for SerDes IO interface. Currently, CC leads SerDes team as a Director of Analog/Mixed-Signal Design at Silicon Creations in Atlanta, Georgia. Before joining Silicon Creations, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta, Georgia, and he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support.
Chung-Chun (CC) Chen (S’02–M’09–SM’17) was born in Taipei, Taiwan, in 1979. He received a B.S. degree in the Institute of Electrical and Control Engineering at National Chiao Tung University, Hsinchu, Taiwan, in 2002, M.S. and Ph.D. degrees in Communication Engineering and Electrical Engineering from National Taiwan University, Taipei, Taiwan, in 2004, and 2009, respectively. His current research interests focus on circuit designs in clocking and other SerDes building blocks for high-speed communication systems. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.
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