Gary Giust - How to specify refclk jitter for SerDes applications
Abstract: The public’s appetite for data is creating enormous demand for high-speed connectivity. But as data rates increase, timing margins decrease. Specifically, as data rates double, the timing margin, or jitter, allocated to a system must cut in half. At the heart of timing, reference clocks (refclks) are used to time data in a communications channel. As such, the refclk consumes a portion of the overall system jitter budget. This talk discusses the evolution of refclk jitter from a standards perspective, focusing on the latest developments in PCI Express and its implication for the timing and SerDes industries in general. We explain the need to move from oscilloscope to phase-noise analyzer measurements of refclk jitter, how to technically account for their differences, and propose a methodology, or template, for SerDes vendors to specify refclk jitter in their datasheets. Widespread adoption of this methodology enables SerDes vendors and their customers to optimize link performance while simplifying refclk selection.
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- AGH University
- Kraków, Malopolskie
- Poland 30-059
- Building: B-1
- Room Number: 121
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- Co-sponsored by Silicon Creations
Speakers
Gary Giust of SiTime
Biography:
Gary Giust, PhD, heads technical marketing at SiTime working with customers to optimize timing at the architectural level. Prior to SiTime, Giust founded JitterLabs, and previously worked at Applied Micro, PhaseLink, Supertex, Cypress Semiconductor, and LSI Logic. Giust is an industry expert on timing, has co-authored a book, is an invited speaker, an internationally published author in trade and refereed journals, and a past Technical Chair for the Ethernet Alliance's backplane subcommittee. He holds 20 patents. Giust obtained a Ph.D. at Arizona State University, Tempe, an MS at the University of Colorado Boulder, and a BS at the University of New Hampshire, Durham, all in electrical engineering.
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