IEEE SSCS Chapter Poland Meeting - Course on Microelectronics by Willy Sansen
During IEEE SSCS Chapter Poland Meeting Prof. Willy Sansen will give 2-day course on "Circuits with resistor and capacitor cancellation: design techniques to enhance high-frequency performance without increased power consumption".
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- AGH University of Science and Technology
- Av. Mickiewicza 30
- Cracow, Malopolskie
- Poland 30-059
- Building: B1
- Room Number: 121
- Click here for Map
Speakers
Willy Sansen
Circuits with resistor and capacitor cancellation: design techniques to enhance high-frequency performance without incre
Willy Sansen received a PhD degree from U.C.Berkeley in 1972. Since 1980 he has been full professor at the Catholic University of Leuven, in Belgium. From 1984 to 2008, he has headed the ESAT-MICAS laboratory on analog design, which has created six spinoffs in the last fifteen years. He has been supervisor of sixty-four PhD theses and has authored and coauthored more than 650 publications and fifteen books among which the Powerpoint slide based book “Analog Design Essentials” (Springer 2006). He has been involved in several spinoffs of the KULeuven and is a member of several Boards of Directors. He is a member of several editorial and program committees of journals and conferences. He was Program chair of the ISSCC-2002 conference and President of the IEEE Solid-State Circuits Society in 2008-2009. He is the recipient of the D.O. Pederson award of the IEEE Solid-State Circuits in 2011. He is a Life Fellow of the IEEE.
Willy Sansen
Circuits with resistor and capacitor cancellation: design techniques to enhance high-frequency performance without incre
Biography:
Agenda
Monday, Oct. 12th, 2015, 9.00-10.30, building B1, room 121
1.1 Minimum-power amplifying stages
Single-transistor stages determine the performance for high-frequency blocks such as LNA’s and VCO’s. Moreover they determine the gain, which can be realized in nanometer CMOS transistor stages. The gain, input and output impedance is analyzed of the three single-transistor stages i.e. the amplifier, the source follower and the cascode. In addition the current consumption is minimized of the amplifying stage using EKV/BSIM6 models.
Monday, Oct. 12th, 2015, 11.00-12.30, building B1, room 121
1.2 Differential amplifying blocks with positive feedback
Practical designs are built up by means of differential pairs, current sources and two-transistor cascodes. They are analyzed in details followed by fully-differential voltage and current amplifiers. Positive feedback is added as well to enhance both the Gain and the Gain-Bandwidth. Design procedures are discussed in all regions of operations (from weak to strong inversion and velocity saturation).
Monday, Oct. 12th, 2015, 13.30-15.00, building B1, room 121
1.3 High-frequency and RF design techniques
Real high-frequency performance can be reached up to fT/3 even if all parasitic components are included. In addition feedforward and pole-zero compensation schemes can be adopted to extend the frequency range. Many examples are given and discussed.
Monday, Oct. 12th, 2015, 15.30-17.00, building B1, room 121
1.4 Examples of low-noise design
Low-noise design techniques are applied to amplifier configurations, filters and LNA’s. Indeed wireless receivers all start with a LNA (Low-noise amplifier) to provide limited gain but with low noise and distortion. The most recent ones are all wide-band, and use both noise and distortion cancellation, which yields higher FOM’s than hitherto possible.
Tuesday, Oct. 13th, 2015, 9.00-10.30, building B1, room 121
2.1 Compensation techniques in operational amplifiers
Two-stage operational amplifiers in unity-gain configuration, suffer from peaking unless a compensation capacitance is added, or the current is increased in the second stage. These stability conditions are examined followed by three techniques to get rid of the positive zero. These design plans are extended to three-stage amplifiers with nested Miller compensation.
Tuesday, Oct. 13th, 2015, 11.00-12.30
2.2 Most-important opamp configurations
In practice only a few amplifier configurations are used. Examples are the symmetrical amplifier, the folded-cascode and the Miller OTA amplifier. In this presentation, all of them are optimized with respect to power consumption, high-speed capability and noise. The compromises are discussed in detail and a comparison is provided. In addition, some specific design techniques such as negative resistors, are reviewed to enhance performance.
Tuesday, Oct. 13th, 2015, 13.30-15.00, building B1, room 121
2.3 Design of multistage operational amplifiers
Two-stage amplifiers may not provide sufficient gain and or frequency performance in nanometer CMOS technologies. This is why three-stage amplifiers have become necessary. This is also true for most power amplifiers in which two preceding stages are required for high gain. The stability is analyzed of such amplifiers. It is shown that three-stage amplifiers can provide tracking pole-zero compensation, which results in lower power consumption than a two-stage amplifier with similar performance.
Tuesday, Oct. 13th, 2015, 15.30-17.00, building B1, room 121
2.4 Opamps, Gm-block or Inverters for filters
Operational amplifiers have been the backbone of most amplifiers and filters in communication applications and ADCs. They are in competition with Gm blocks for higher frequencies despite their higher linearity. Both of them are now gradually being replaced by CMOS inverters. This presentation focuses on the merits and advantages of all three of them.