Shiuh-hua Wood Chiang

The demand for high-speed, low-power analog-to-digital converters (ADCs) for high-speed wireline transceivers and mmWave radios continues to grow unabated, driven in part by advances in DSP-based architectures and technology-scaling benefits in digital circuits. Recent works on high-speed ADCs operating at > 10 GHz with 6 to 8 bits of resolution have made tremendous progress, but significant challenges remain. This talk discusses techniques to achieve simultaneous high speed and high power efficiency by using the time-interleaved successive-approximation-register (SAR) architecture. We present “constant-matching scaling” and “grouped capacitors” for the digital-to-analog-converter (DAC) to aggressively reduce the capacitance and increase the speed. The ADC also demonstrates a “dual-path” bootstrapped switch to increase the sampling spurious-free dynamic range (SFDR). Employing the above and other low-power, high-speed techniques, the proposed SAR ADC obtains a single-channel speed of 1.25-GHz without the need for pipelining. The ADC uses only 8X time-interleaving to achieve an overall sampling rate of 10 GHz and a signal-to-noise-and-distortion ratio (SNDR) of 36.9 dB at Nyquist while consuming 21 mW.

Biography:

Shiuh-hua Wood Chiang received his B.S. degree in Computer Engineering from the University of Waterloo, Waterloo, Canada in 2007, the M.S. degree in Electrical Engineering from the University of California, Irvine in 2009, and the Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2013. He was a Postdoctoral Scholar in the Communication Circuits Laboratory at the University of California, Los Angeles in 2013. From 2013 to 2014 he was a Senior Design Engineer in Qualcomm. He joined the Department of Electrical and Computer Engineering of Brigham Young University in 2014. His research interests include low-power RF/analog/mixed-signal circuits for communications and sensing applications.

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