Accelerating Visual Analytics across the Memory and Storage Stack

#data #analytics #processing-in-memory #vlsi

Data analytics involves the discovery of patterns and complex relations in data to assist with effective decision-making. Such analytics are applied on a variety of data forms such as video streams, financial data, social media messages, and sensor information from smart homes and personal health monitoring devices. However, data analytics is becoming exceedingly challenging as the generated volume of data is increasing exponentially. Co-design across the stack from materials to architectures will be vital to addressing crosscutting challenges posed by the enormity of data that needs to be processed. This talk will showcase such optimization targeted at visual analytic applications such as Deep Neural networks, graph analytics and query support.

First, I will present a Look-Up Table (LUT) based Processing-In-Memory (PIM) technique with the potential for running Neural Network inference tasks.  The proposed LUT-based PIM methodology exploits substantial parallelism using look-up tables that preserve the bit-cell and peripherals of the existing SRAM monolithic arrays in processor caches. Next, I will present GaaS-X, a graph analytics accelerator that inherently supports sparse graph data representations using in-situ compute-enabled crossbar memory architectures. The proposed design alleviates the overheads of redundant writes, sparse to dense conversions, and redundant computations on the invalid edges that are present in other state-of-the-art crossbar-based PIM accelerators. Finally, I will present an in-SSD key-value database that uses the embedded CPU core, and DRAM memory on the SSD to support various queries with predicates and reduce the data movement between SSD and host processor significantly.

• Date: 20 Jun 2023
• Time: 08:30 AM to 10:00 AM
• All times are (UTC-03:00) Montevideo
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• Julio Herrera y Reissig 565
• Montevideo, Montevideo
• Uruguay
• Building: Facultad de Ingeniería
• Room Number: Laboratorio de Software del IIE

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• Co-sponsored by Grupo de Microelectrónica, Facultad de Ingeniería, Universidad de la República