From Transistor Scaling to 2D Materials: A Journey into Nanoelectronics
The rapid development of the nano-electronic industry over the past decades has relied on the process of transistor scaling to provide significant improvements to transistor performance at a reduced cost. Multiple directions have been pursued to extend the semiconductor industry's growing trend, including searching for new material systems, designing new transistor structures, demonstrating new functionalities, and developing new applications. The semiconductor chip has two main elements: active devices (i.e., transistors) and interconnects. As for active devices, new 2-D materials (MoS2, WS2, BN, etc.) are all aggressively studied to realize high energy efficiency and memory/logic functions for system compactness. Since the discovery of graphene in 2004, researchers have focused on layer-structured materials and their applications in electron devices. This talk will present the current status and possible application developments in nanoelectronics and nanomaterials. A brief introduction is discussed to the general nanoelectronics and 2D materials for device applications. The technical challenges of 2D materials are discussed. This talk will introduce various technologies that are based on 2D materials and will be discussed possible applications. In addition, traditional silicon-based devices and the nanotechnology-enabled high-performance device will be discussed.
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- Date: 30 Aug 2023
- Time: 10:30 PM UTC to 12:00 AM UTC
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- Co-sponsored by Northern Virginia/Washington Chap,ED15,SSC37,EP21
Speakers
Prof. Jeongwon Park of University of Nevada Reno, Nevada 89557
From Transistor Scaling to 2D Materials: A Journey into Nanoelectronics
The rapid development of the nano-electronic industry over the past decades has relied on the process of transistor scaling to provide significant improvements to transistor performance at a reduced cost. Multiple directions have been pursued to extend the semiconductor industry's growing trend, including searching for new material systems, designing new transistor structures, demonstrating new functionalities, and developing new applications. The semiconductor chip has two main elements: active devices (i.e., transistors) and interconnects. As for active devices, new 2-D materials (MoS2, WS2, BN, etc.) are all aggressively studied to realize high energy efficiency and memory/logic functions for system compactness. Since the discovery of graphene in 2004, researchers have focused on layer-structured materials and their applications in electron devices. This talk will present the current status and possible application developments in nanoelectronics and nanomaterials. A brief introduction is discussed to the general nanoelectronics and 2D materials for device applications. The technical challenges of 2D materials are discussed. This talk will introduce various technologies that are based on 2D materials and will be discussed possible applications. In addition, traditional silicon-based devices and the nanotechnology-enabled high-performance device will be discussed.
Biography:
Dr. Park joined the Department of Electrical and Biomedical Engineering at the University of Nevada, Reno, NV, USA as an Associate Professor in July 2019. Prior to that, he was an Associate Professor at the School of Electrical Engineering and Computer Science at the University of Ottawa, Canada (2016-2021, currently: Adjunct Professor) and a scientist at SLAC National Accelerator Laboratory, Stanford University, USA (2014 -2016). For six years (2008-2014), he served as a senior technologist to support the corporate chief technology officer (CTO) and business units at Applied Materials, USA. In addition, he has been a guest researcher at the Lawrence Berkeley National Laboratories (2005-2008), an adjunct professor in the Department of Electrical Engineering at Santa Clara University (2009-2016), and a visiting scholar in the Department of Electrical Engineering at Stanford University, CA, USA (2013-2014). He received his Ph.D. (2008) in materials science and engineering from the University of California, San Diego, USA. He is a senior member of IEEE.
Email:
Address:University of Nevada, , Reno, Nevada , United States, 89557