Tutorial: Thermal Challenges for Heterogeneous Integration Packaging

#heterogeneous #integration #thermal #cooling #packaging #2D #3D

-- thermal management, hot spots, heat transfer, 2.5D & 3D, simulation, examples ...

Heterogeneous Integration poses several significant challenges for thermal management at multiple length scales ranging from heat extraction from hot spots, heat transfer through multiple layers of materials, different target temperatures for specific devices/materials, to heat rejection to a system cooling solution or the ambient. This applies to system-in-packages, including 2D, 2.5D, and 3D subsystems and the special needs of photonic devices. We need to consider the various thermal paths within packages to dissipate the generated heat, how to apply modeling and simulation, and advanced cooling methods including conduction, liquid cooling, heat pipes, and more exotic designs.
It is important to identify and develop a detailed understanding of the capabilities and limitations of key thermal technologies that meet or exceed these demands so that they are available well in advance of need and can be implemented if they meet integration cost envelopes. We will consider three areas for thermal management: Die level; Package integration/System-in-Package (SIP)/module level; and System level. We will focus on emerging challenges and opportunities for thermal modeling of advanced 3D IC systems; challenges and characterization of hotspot modeling; thermal modeling for High Bandwidth Memory (HBM) and integrated voltage regulators; and innovative methods for manufacturing silicon microchannels.

Then, we will consider an advanced design example.  Sustainable and efficient operation of US data centers, currently consuming ~100 billion kWh/year, requires transformative and innovative technologies. Nearly 20% of the total power is used to run the data center refrigeration cooling infrastructure, which is extremely sensitive to climate and environmental conditions. The ever-increasing prevalence of higher-power processors aggravates cooling/energy challenges.  It is expected that reducing the thermal resistance of the device junction to coolant by 10×, will pave the way for elimination of refrigeration cooling systems, resulting in considerable energy saving in the data centers.  
In the case of two-phase flow, flow instability and large superheat are major concerns that must be addressed: pressure drop, hotspot cooling, larger chip areas, and liquid films on heat walls.  The enhanced cooling <strong>IceCool Fundamentals</strong> initiative by DARPA, and several ARPA-e recent initiatives, resulted in development of a series of remarkable thermal management solutions for very challenging performance metrics targets.

  Date and Time




  • Date: 02 Nov 2023
  • Time: 08:00 AM to 09:30 AM
  • All times are (UTC-07:00) Pacific Time (US & Canada)
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  • Starts 28 September 2023 04:17 AM
  • Ends 02 November 2023 09:17 AM
  • All times are (UTC-07:00) Pacific Time (US & Canada)
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Tiwei Wei Tiwei Wei of Purdue University


Professor Tiwei Wei is the Principal investigator for the Purdue Semiconductor Packaging Laboratory (All-in-one for Semiconductor Packaging, Heat transfer, and Assembly Lab) Semiconductor Packaging Laboratory.  It's Vision: Focus on the processing, materials, and architecture development for future advanced semiconductor interconnects and 2.5D/3D packaging, as well as efficient thermal management technologies and reliability characterizations. The applications cover microelectronics chips, LED, power electronic modules, Photonics, Quantum computing, and X-ray and high-power laser optics. He was a PhD Researcher at imec, and completed a post-doc at Stanford University. He chairs the Central Indiana EPS chapter.

Mehdi Asheghi Mehdi Asheghi of Stanford University


Professor Mehdi Asheghi was a founding member of the Nanoheat research group at Stanford University in 1994. He completed his Ph.D. and postdoctoral studies at Stanford through research on nanoscale thermal engineering of microelectronic devices, including several highly cited papers on phonon conduction in silicon layers. He led a very well funded research program at Carnegie Mellon University (2000-2006) that focused on nanoscale thermal phenomena in semiconductor and data storage devices. At Stanford his research ranges from nanoscale memory technologies to two phase microfluidics. Dr. Asheghi is the author of more than 200 journal publications, fully-reviewed conference papers, and book chapters, and was technical program and was technical program and general chairs at ITherm 2012, 2014 and InterPACK 2015 and 2017.