Novel Chiplet Connectivity Technologies For Enabling High-end AI/HPC
Technical Seminar by Dr. Ramin Farjadrad with the following abstract:
For the past 4 decades, industry has supported 2x conpute performance increase every 2 years, a trend supported by Moore’s Law. However, not only has Moore’s law come to an end, but also the exponential demand for more AI/HPC had driven the performance demand close to 10x/year. This recent trend has resulted in the chips growing significantly in size, to include more compute cores, exceeding maximum chip manufacturing dimensions.
The chiplet system-in-package (SiP) enables implementing very large processor chips by connecting several smaller chiplets. These chiplets must be connected at very high bandwidth and low power, to perform like a single chip. Advanced packaging technologies like silicon interposers are developed to connect chiplets at the target bandwidths/powers. However, advanced packaging solutions, besides being super expensive, come with many limitations. A major limitation is their supply chain. Currently, TSMC is the sole provider of large Silicon Interposers that are critical for AI/HPC chips. Even without any geopolitical risk that may limit TSMC’s suppl, TSMC cannot deliver the worldwide interposer demand in near future.
This presentation introduces novel chiplet connectivity technologies that enables creating high-end AI/HPC chips without the need for large interposers.
Date and Time
Location
Hosts
Registration
- Date: 24 Oct 2023
- Time: 10:00 AM to 11:00 AM
- All times are (UTC-07:00) Pacific Time (US & Canada)
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- Vancouver, British Columbia
- Canada
- Starts 18 October 2023 06:00 PM
- Ends 24 October 2023 10:10 AM
- All times are (UTC-07:00) Pacific Time (US & Canada)
- No Admission Charge
Speakers
Ramin Farjadrad of Eliyan
Novel Chiplet Connectivity Technologies For Enabling High-end AI/HPC
Abstract:
For the past 4 decades, industry has supported 2x conpute performance increase every 2 years, a trend supported by Moore’s Law. However, not only has Moore’s law come to an end, but also the exponential demand for more AI/HPC had driven the performance demand close to 10x/year. This recent trend has resulted in the chips growing significantly in size, to include more compute cores, exceeding maximum chip manufacturing dimensions.
The chiplet system-in-package (SiP) enables implementing very large processor chips by connecting several smaller chiplets. These chiplets must be connected at very high bandwidth and low power, to perform like a single chip. Advanced packaging technologies like silicon interposers are developed to connect chiplets at the target bandwidths/powers. However, advanced packaging solutions, besides being super expensive, come with many limitations. A major limitation is their supply chain. Currently, TSMC is the sole provider of large Silicon Interposers that are critical for AI/HPC chips. Even without any geopolitical risk that may limit TSMC’s suppl, TSMC cannot deliver the worldwide interposer demand in near future.
This presentation introduces novel chiplet connectivity technologies that enables creating high-end AI/HPC chips without the need for large interposers.
Biography:
Ramin Farjadrad is the founding CEO of Eliyan, a company focused on next generation chiplet-based system-in-package (SiP) solutions. He was previously the CTO/VP of Networking/Automotive Connectivity at Marvell Technologies, in charge of developing technologies for autonomous vehicles, hyperscale data centers, and heterogenous SiP Integration. Ramin co-founded two technology companies, Velio Communications that was acquired by Rambus/LSI Logic, and Aquantia that IPO’d in 2017 and was acquired by Marvell in 2019. Ramin has pioneered a number of connectivity technologies adopted as international standards, such as Multi-Gig Automotive Ethernet (IEEE 802.3ch), Enterprise Ethernet (IEEE 802.3bz), and the BoW die-to-die connectivity at OCP. He is the author of over 140 granted/pending patents. He earned his Masters and PhD in electrical engineering from Stanford University.
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