“How and Why 2.5D and 3D Integration is Revolutionizing Silicon Design”
Abstract:
For decades, Moore’s Law has delivered the ability to integrate an exponentially increasing number of devices in the same silicon area at a roughly constant cost. This has enabled tremendous levels of integration, where the capabilities of computer systems that previously occupied entire rooms can now fit on a single integrated circuit.
In recent times, the steady drum beat of Moore’s Law has started to slow down. Whereas device density historically doubled every 18-24 months, the rate of recent silicon process advancements has declined. While improvements in device scaling continue, albeit at a reduced pace, the industry is simultaneously observing increases in manufacturing costs. In response, the industry is now seeing a trend toward reversing direction on the traditional march toward more integration. Instead, multiple industry and academic groups are advocating that systems on chips (SoCs) be “disintegrated” into multiple smaller “chiplets.” This talk details the technology challenges that motivated AMD to use chiplets, the technical solutions we developed for our products, and how we expanded the use of chiplets from individual processors to multiple product families. From this foundation, we will look toward the future of chiplet and 3D architectures that will require multi-disciplinary innovation across package technology, silicon design, accelerators, and the software to exploit them.
Date and Time
Location
Hosts
Registration
- Date: 16 Nov 2023
- Time: 06:30 PM to 08:30 PM
- All times are (UTC-07:00) Mountain Time (US & Canada)
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- 1075 Woodward Way
- Woodward Corporate Campus
- Fort Collins, Colorado
- United States 80524
- Building: Coy Barn Conference Center
- Click here for Map
- Starts 30 October 2023 09:30 AM
- Ends 14 November 2023 05:00 PM
- All times are (UTC-07:00) Mountain Time (US & Canada)
- No Admission Charge
Speakers
Samuel
2.5D and 3D Integration
Biography:
Samuel Naffziger is SVP and Corporate Fellow at AMD responsible for technical strategy and product architecture. He has been the lead innovator behind many of AMD’s low power features and chiplet architecture. He has over 35 years of industry experience with a background in microprocessors and circuit design, starting at Hewlett Packard, moving to Intel and then at AMD since 2006. He received the BSEE from CalTech in 1988 and MSEE from Stanford in 1993 and holds over 150 US patents in the field. He has authored dozens of publications and presentations on processors, architecture and power management and is a Fellow of the IEEE.
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