Tech Talk on VLSI design and career opportunities
The IEEE Student Branch BIT organized an enlightening tech talk on Very Large Scale Integration (VLSI) on 20th November. The event aimed to explore the intricacies of VLSI design and shed light on diverse career paths in this field. The event was presided by Dr Ashwath MU, our esteemed Principal, Dr. Hemanth Kumar AR, Head of department, Electronics and Communication Engineering and Dr Jalaja S, IEEE SB Counselor along with speaker of the day Dr G S Javed.
Dr G S Javed is an accomplished Analog IC Design manager with over 14 years of experience at Intel India. Dr Javed shared valuable insights into the design, layout, and characterization of Analog Circuits, serving as the Technical and Execution Lead
- Analog at Intel India. Dr Javed initiated the talk by providing a comprehensive overview of VLSI, its applications, and its significance in the tech industry. The event drew a robust attendance with over 50 participants hailing from various branches, primarily the VLSI branch. The event was executed with a budget of Rs.5000, demonstrating the IEEE Student Branch BIT's efficient use of resources to deliver a valuable and impactful experience for participants.
The participants gained insights into various career opportunities within the VLSI domain, exploring pathways for personal and professional growth. There was also an interactive quiz testing the knowledge of the participants and the event concluded with a Q and A session with the speaker where the participants had a chance to personally interact with the speaker and get their doubts cleared.
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- Bangalore Institute Of Technology, Department Of Electronics And Communication, Kr Road, Vv Pura
- Bangalore, Karnataka
- India 560004
- Starts 13 November 2023 11:53 AM UTC
- Ends 19 November 2023 11:53 AM UTC
- No Admission Charge