Seventh Annual Symposium on Heterogeneous Integration Roadmap and Annual Meeting

#HIR #packaging #electronics #integration

Future Vision for Heterogeneous Integration from Global Perspectives, 2 days, 8 keynote talks, working groups ...

 [see details in AGENDA box below]


When you get to the Visitor Parking area, staff will guide you to available section, and to the South Tower to check in and get ypour badge.



  Date and Time




  • Start time: 21 Feb 2024 01:00 PM
  • End time: 23 Feb 2024 05:00 PM
  • All times are (UTC-08:00) Pacific Time (US & Canada)
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  • Samsung Electronics Campus
  • 3655 N First Street,
  • San Jose, California
  • United States 95134

  • Contact Event Host
  • Starts 04 January 2024 06:30 PM
  • Ends 23 February 2024 05:00 PM
  • All times are (UTC-08:00) Pacific Time (US & Canada)
  • 3 in-person spaces left!
  • Admission fee ?
  • Menu: Vegetarian, Halal/ Kosher, No preference, Other - contact organizer






William Chen (Bill) holds the position of ASE Fellow & Senior Technical Advisor at ASE Group. Prior to joining the ASE, he was Director at the Institute of Materials Research & Engineering (IMRE) in Singapore, following a distinguished career at IBM Corporation. Bill is a past President of the IEEE Electronics Packaging Society. He is a Life Fellow of IEEE and a Fellow of ASME. He received the ASME InterPACK Achievement Award in 2007. In 2018, he received the IEEE Electronics Packaging Field Award, recognizing his contribution to electronics packaging, from research & development through industrialization.

Bill chairs the Heterogeneous Integration Roadmap (HIR) initiative, co-sponsored by IEEE Electronics Packaging Society, SEMI, IEEE Electron Devices Society, IEEE Photonics Society & ASME Electronics & Photonics Packaging Division

Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes including 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi joined Intel in 1992 after earning his Ph.D. in Mechanical Engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE.  He was elected to the National Academy of Engineering in 2022 for contributions to advanced microelectronics packaging architectures and their thermal management.

S.V. Sreenivasan, Ph.D. is the Cockrell Family Regents Chair #7 in Engineering at The University of Texas at Austin. He is the director of the NSF funded NASCENT Center, and Founder and Chief Technology Officer of the Texas Institute for Electronics, Inc.. He also co-founded Molecular Imprints Inc. (MII), a nanopatterning spin out from UT-Austin. The semiconductor business of MII was acquired by Canon Corporation, and the display division of MII was acquired by Magic Leap, Inc. Sreenivasan earned a Bachelor of Technology from the National Institute of Technology at Tiruchirappalli, and a Ph.D. from The Ohio State University

Dr. Melissa Grupen-Shemansky currently serves as Chief Technical Officer (CTO) at SEMI and Vice President of Technology Communities.  Technology Communities at SEMI are industry groups of varying disciplines critical to the microelectronics supply chain that are assembled to address opportunities and challenges best address collectively. Technology community collaboration results in sharing of best practices, development of roadmaps, and publication of standards, as a few examples. In addition, Dr. Grupen- Shemansky is responsible for program oversight of consortium R&D projects that are in-part funded by the Department of Defense.  Presently, there are three public-private partnerships addressing flexible hybrid electronics (FHE), nano-bio applications (NBMC), and positioning, navigation, and timing (PNT).  The consortia represent over $160M in federal and industrial investment over the span of 8 years furthering the advancement of U.S. microelectronics technologies and ecosystem development. Dr. Grupen-Shemansky is also CEO of the FlexTech Alliance, Inc., a not-for-profit subsidiary of SEMI responsible for the Manufacturing Innovations Institute, NextFlex.

Dr. Nicky Lu, a prominent technology innovator and serial entrepreneur, is CEO/ Founder of Etron Technology, which was established in 1991. He co-founded successful companies like Ardentec and Global Unichip. Dr. Lu's career includes significant contributions to the semiconductor industry, notably at IBM, where he received an IBM Corporate Award and received the IEEE Highest Technical Award in Solid-State Circuits, solidifying his esteemed status.

He's credited with creating Taiwan’s first 8-inch-wafer and advanced Logic/4MbSRAM/16MbDRAM products, thus advancing Taiwan's semiconductor industry. In the early 2000s, Dr. Lu pioneered "Known-Good-Die and Heterogeneous Integration of Technologies," which has received an Intel’s Preferred Quality Supplier Award and has since become a cornerstone of current and future chip developments. With a Ph.D. from Stanford University, he is a member of NAE, NAI, and an IEEE Fellow, with 56 US patents, 60+ technical papers, and key roles like chairing the World Semiconductor Council (2014-15) and the Taiwan Semiconductor Industry Association (2013-17). He has also chaired the AI-on-Chip Taiwan Alliance since 2019 and has founded several AI and Data-Privacy companies.




“Learning from the National Advanced Packaging Manufacturing Program (NAPMP)”

Subramanian S. Iyer has joined CHIPS for America’s Research and Development (R&D) Office as the director of the National Advanced Packaging Manufacturing Program (NAPMP). Iyer brings extensive industrial and academic experience and expertise in microelectronics and packaging.

Iyer comes to CHIPS via an Intergovernment Personnel Act (IPA) agreement with the University of California, Los Angeles (UCLA), where he is a distinguished professor and holds the Charles P. Reames Endowed Chair. Under the IPA, Iyer remains an employee of UCLA while on full-time assignment to the CHIPS R&D Office.

At UCLA, Iyer’s teaching and research interests are in exploring new packaging paradigms and device innovations that may enable high-performance architectures, in-memory analog compute, and medical engineering applications. 

Panel / Fireside Chat with invited guest panelists

Timothy Lee, currently a Boeing Technical Fellow, is responsible for the development of RF and digital electronics for advanced communications networks and sensor systems. In the IEEE, Tim is promoting the use of technology to benefit humanity. He is IEEE Region 6 Director, IEEE Future Networks Initiative  Co-Chair, IEEE HIR, A-D & AMS TWG Co-Chair, and Past President of IEEE MTTS. He is the President Elect of IEEE USA.


Ajit Manocha is president and CEO of SEMI, the global industry association serving the electronics manufacturing and design supply chain. Throughout his career, Manocha has been a champion of industry collaboration as a critical means of advancing technology for societal and economic prosperity.

Manocha was formerly CEO at GlobalFoundries. Prior to this he held the role of executive vice president of worldwide operations at Spansion and earlier served as EVP and chief manufacturing officer at Philips/NXP Semiconductors. He began his career as a research scientist at AT&T Bell Laboratories where he was granted more than a dozen patents related to semiconductor manufacturing processes.

Manocha has served on the President’s committee for “Advanced Manufacturing Partnerships” and the President’s Council of Advisors on Science & Technology (PCAST). More recently, VLSIresearch added Manocha to its Semiconductor Industry Hall of Fame, and he was inducted into the Silicon Valley Engineering Hall of Fame.


Day 2 Keynotes


Dr. Vincent (WooPoung) Kim is the Corporate EVP, Head of Advanced Packaging at Samsung Device Solutions Research America based in San Jose, California.

Dr. Kim is responsible for leading the Advanced Packaging (AVP) division at Samsung Semiconductor, which is a newly launched business unit dedicated to meeting industry needs for advanced chip packaging in high-performance systems. Prior to joining Samsung, he served as a System Architect for Signal Integrity and Power Integrity at Apple, where he played a crucial role in developing consumer computers. Before his tenure at Apple, Dr. Kim worked as an SI Manager in Snapdragon packaging at Qualcomm. Prior to that, he was a Co-Design Engineer in the Wireless Business Unit of Texas Instruments, where he specialized in optimizing the electrical design of OMAP packages and systems. Dr. Kim also gained valuable experience as an SI Engineer at Rambus, where he designed and analyzed memory systems.

Dr. Kim received his Ph.D degree in Electrical and Computer Engineering (ECE) at Georgia Tech in 2004, and his M.S. & B.A. degrees from KAIST, Korea in 1999 and 1997. 

“AMD InstinctTM MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems”

Alan Smith is an AMD Sr. Fellow and Instinct lead SoC architect specializing in large scale datacenter GPU accelerated SoCs.  Focused on advanced development of System in package and scale-up, scale-out system architectures for exescale AI and HPC systems, including optimizations of IP and SOC technologies and architectures for power constrained performance.  Expert in NoC, memory and cache architectures for multi-stack HBM SOC’s optimized for low energy per bit delivered into GPU accelerated computing engines, advanced 2.5D and 3D packaging technologies and trade-offs for performance, product cost and manufacturing.


“Challenges and Opportunities in Manufacturing 3-Dimensional Heterogeneously Integrated (3DHI) Microsystems”

Dr. Carl E. McCants is a special assistant to the DARPA director, focusing on efforts to inform microelectronics policy and national strategies for microelectronics research and development.

Prior to his role at DARPA, he was the technical director of the Supply Chain and Cyber Directorate of the National Counterintelligence and Security Center (NCSC), in the Office of the Director of National Intelligence and a senior program manager at the Intelligence Advanced Research Projects Activity (IARPA).

From 2010 to 2012, he was a program manager in the Microsystems Technology Office at DARPA, focused on microelectronic integration and hardware assurance and reliability. From 2003 to 2009, he served as the chief technologist to the director of MTO, and special assistant to the DARPA deputy director.

From 1999 to 2003, McCants was a project manager at Agilent Technologies’ Semiconductor Products Group, and from 1988 to 1999, he was a development engineer at Hewlett-Packard’s Optical Communication Division.

McCants received his bachelor’s degree from Duke University in 1981 and his master’s and doctoral degrees from Stanford University in 1982 and 1989, respectively, all in electrical engineering. He is a senior member of the IEEE.




Wei-Chung(Robert) Lo, Deputy General Director of Electronic and Optoelectronic System Research Laboratories(EOSL) of ITRI. Dr. Lo received his Ph.D. from National Taiwan University and joined Industrial Technology Research Institute to work in advanced electronic packaging, such as WLP, 3D IC/3D stacking, fan-out, heterogeneous integration technology for more than 20 years, 85 papers and 27 patents granted.

Dr. Robert W. Wisniewski is a Senior Vice President, Chief Architect of HPC, and the Head of Samsung's SAIT Systems Architecture Lab.  He is an ACM Distinguished Scientist and IEEE Senior Member.  The System Architecture Lab is innovating technology to overcome the memory and communication walls for HPC and AI applications.  He has published over 80 papers in the area of high performance computing, computer systems, and system performance, has filed over 62 patents with over 46 issued, has an h-index of 42 with over 7500 citations, and has given over 85 external invited presentations.  Prior to joining Samsung, he was an Intel Fellow and CTO and Chief Architect for High Performance Computing at Intel.  He was the technical lead and PI for Aurora, the supercomputer delivered to Argonne National Laboratory as one of the world's first exascale computers.  He was also the lead architect for Intel's cohesive and comprehensive software stack that was used to seed OpenHPC, and served on the OpenHPC Governance Board as chairman.  Before Intel, he was the chief software architect for Blue Gene Research and manager of the Blue Gene and Exascale Research Software Team at the IBM T.J. Watson Research Facility, where he was an IBM Master Inventor and led the software effort on Blue Gene/Q, which received the National Medal of Technology and Innovation, was the most powerful computer in the world in June 2012, and occupied 4 of the top 10 positions on the Top 500 list.

“Future architecture demands for more aggressive packaging”

Josh Fryman, Intel Fellow, drives advanced R&D programs at Intel’s CTO office for future technology development.  Josh is a PI for many DARPA, DOE, and IARPA programs driving breakthroughs in co-packaged optical IO, advanced memories, and novel compute. Josh obtained his BS in computing engineering from UF, and his PhD in computer architecture from GaTech.”

Erik Jung has a background in “physics”, “physical chemistry” and “physics in medicine” from the University of Kaiserslautern, he joined Fraunhofer IZM in 1994. Heading the group Advanced Microsystem Assembly, he developed processes in flip chip and chip embedding technologies eventually expanding his research field into the MEMS/NEMS packaging and initiated IZM´s MEMS research program in 2005.

Staying from 2007 to 2008 as a research delegate at the University of Utah he was involved in the packaging of a wireless brain computer interface, establishing the focus group on Medical Microsystems upon his return to the Fraunhofer IZM. He was appointed as head of the business sector on medical technologies in 2009.


Wednesday February 21, 2024

1:00 pm to 4:00 pm

Learning from the National Advanced Packaging Manufacturing Program (NAPMP)

Keynote Presentation from Professor Subramanian S. Iyer, Director, National Advanced Packaging Manufacturing Program (NAPMP)

Panel / Fireside Chat with three guest panelists

Ajit Manocha - SEMI President

Nicky Lu – CEO/ Founder ETRON

Tim Lee – IEEE USA President Elect & Boeing Fellow

Q&A from the floor


Ravi Mahajan & William Chen

Thursday February 22, 2024

9:00 am to 12:00 noon

Conference Opening Welcome

HIR Technology Focus and Future Vision

Keynote Speakers

Dr Vincent (Woopoung) Kim (Samsung)

Advanced Packaging in the Era of HPC and AI”

Alan Smith (AMD)

“AMD InstinctTM MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems”

Carl McCants (Darpa)

“Challenges and Opportunities in Manufacturing 3 dimentional Heterogeneously Integrated (3DHI) Microsystem”

John Schreck & S.V. Sreenivasan (TIE UT Austin)

“Creating a Wafer-level 3DHI R&D and Prototyping Facility”


1:15 pm to 4:30 pm

HIR TWG Presentations

Wine Tasting 

Friday February 23, 2024

Wei-Chung Lo/ Shih-Chieh Chang (EOSL-ITRI, Taiwan)

“Collaboration in Advancing Advanced Packaging and Manufacturing in Heterogeneous Integration in ITRI”

Bob Wisniewski (Samsung)

The Importance of Tight Coupling for Performance and Productivity”

Josh Fryman (Intel)

“Future architecture demands for more aggressive packaging”

Erik Jung/ Albert Heuberger (Fraunhofer Institute Germany)

"Advanced Heterogenous Integration as a core activity in the European ChipsJU Initiative"


1:15 pm to 4:30 pm

HIR TWG Presentations

HIR Town Hall

* TWG Panel/ Teams

Team 1 Thursday February 22, 2024

    • Aerospace & Defense: Tim Lee , Dan Blass
    • 5G Communications & Beyond: Tim Lee , Herbert Bennett
    • Thermal Management: Yin Hang, Madhu Iyengar, Azmat Malik, Weihua Tang
    • Co-Design: Jose E. Schutt-Aine
    • Test: Jeorge Hurtarte, Ken Butler
    • Integrated Power Electronics: Patrick McCluskey, Douglas Hopkins

Team 2 Thursday February 22, 2024

    • High Performance Computing & Data Centers: Kanad Ghose, John Shalf
    • 2D-3D Interconnect: Ravi Mahajan
    • Modelling & Simulation: Chris Bailey , Xuejun Fan
    • Wafer Level Packaging: Rozalia Beica , 
    • Automotive: Veer Dhandapani, Vikas Gupta
    • Additive Electronics Manufacturing: Kris Erickson

Team 3 Friday February 23, 2024

  • SiP & Module: Erik Jung, Rolf Aschenbrenner , Klaus Pressel
  • MEMS & Sensors Integration: Benson Chan, Mary-Ann Maher, Shafi Saiyed
  • Advanced Manufacturing & Multi Chip Integration Mark Gerber, Annette Teng & William Chen
  • Supply Chain: Kitty Pearsall, Melissa Grupen Shemansky Paul Trio , Siva Sivasankar
  • Integrated Photonics, Amr Helmy, Bill Bottoms
  • Cyber Security: Sohrab Aftabjahani

Team 4 Friday  February 23, 2024

  • Medical, Health & Wearables: Mark Poliks , Jan Vardaman
  • IoT: Robert Lo Rockwell Hsu
  • Mobile: Benson Chan , William Chen
  • Reliability Abhijit Dasgupta,  Richard Rao & Shubha Sahasrabudhe
  • Emerging Research Devices: Meyya Meyyapan

Parking available onsite: follow signs

WiFi available