Besa Award for Nottingham University
In July of 2023, University of Nottingham Malaysia (UNM) student Chia Yu Hang from the department of Electrical and Electronic Engineering (EEE) won the IEEE Electronic Packaging Society’s (EPS) Best Engineering Student Award (BESA) for his Final Year Project (FYP) entitled “SRAM-based In-Memory Computing”, under the supervision of Prof T. Nandha. The award was presented to him by Dr Eu Poh Leng from the IEEE EPS society at the annual Faculty of Science and Engineering (FOSE) Awards Ceremony held at the Bangi Convention Center, July 22nd, 2023.
Yu Hang’s FYP tackles the problem of limited computer data throughput caused by the physical separation of the computing elements (the CPU) and the memory elements (the RAM) necessitating information exchange between them on a shared-bus. This is traditionally known as the Von Neumann architecture and the resulting limited throughput over the shared bus is called the Von Neumann bottleneck. In 1945, a Hungarian-American computer scientist, John Von Neumann proposed the computer architectural model that currently bears his name and is still the main architecture used on computing systems in production today. Due to the Von Neumann bottleneck, the maximum throughput at which computers can process data is currently limited by the rate of the sequential data exchange on the bus.
In-memory computing (IMC) also known as Processing in Memory (PIM) is an alternative computer architecture paradigm in which the computing elements and the memory elements are combined together in a single chip rather than having them separated and communicating across the system bus. In his FYP, Yu Hang explored the use of SRAM in the application of an IMC application, in particular his project objectives included designing and evaluating an SRAM cell at the circuit level, designing an IMC architecture using the SRAM cross-bar design, designing a multiplier using the newly proposed IMC architecture and comparing his design with the pre-existing designs.
In his project Yu Hang compared his designs to a 10-transistor SRAM design from the literature and subsequently was able to improve the design to an 8-transistor SRAM resulting in a 20% improvement over the state-of-the art.
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