Daphne Chen

As Moore's law nears its physical limits, a next generation device technology which breaks the limits of computing performance and merges the memory hierarchy gap enables high speed and low power computations. Microelectronics composed of new materials and new devices for exploring the advanced paradigms of computing is a pressing need. Among the emerging semiconductor electronics technologies, non-volatile memory (NVM) become the candidate for enabling the highly efficient computing while with nonvolatility for reliable low power information storage. Among non-volatile memories, resistive random-access memory (RRAM) holds great potential because of its simple design, high-speed operation, excellent scalability, and low power consumption. However, the sneak-path current (SPC) through unselected neighboring cells is a major challenge occurring in crossbar RRAM configuration, especially for large memory arrays. To address the sneak path current issue, a selector device (or a threshold switch) integrated with a memory device has been developed. Several bidirectional selector devices have been proposed for bipolar RRAM, such as transistor device, tunneling diode, Schottky diode, and threshold switches. Unfortunately, the additional selector devices i.e. 1S-1R or 1T-1R configuration considerably increase the process complexity and cost. This seminar will introduce the oxide-based one-resistor-only (1R-only) memory cell with built-in self-selectivity, which is applicable without additional selector device integration, while solving the sneak-path issue for high storage class crossbar array configuration in AI applications. In addition, Prof. Ying-Chen Chen will introduce her current developments on oxide-based selectors, helical-shaped dual functional devices, one-time programmable memory, and novel in-space manufacture roadmap for next generation applications.

Biography:

Dr. Ying-Chen (Daphne) Chen is currently an assistant professor in the School of Electrical, Computing and Energy Engineering at Arizona State University, Tempe, Arizona. She received the Ph.D. degree in Electrical and Computer Engineering (ECE) at The University of Texas at Austin in 2019, B.S. and M.S. degree from National Chiao Tung University (Taiwan). Prior to joining ASU, she was the R&D Pathfinding Emerging Memory Engineer at Micron Technology working, and a hardware developer at IBM on emerging memory and future applications. Her primary research focuses on emerging electronics and memory devices for high density storage, new computing, new manufacture, and energy-efficient integrated systems. She was the recipient of Sandia National Laboratory Research Award 2019, and Rising Stars 2017 in EECS.