IEEE EDS Kansai DL -Key considerations for obtaining high performance contact-controlled devices- (IEEE DL, IEEE EDS Kansai Chapter)
(IEEE EDS Kansai DL) Key considerations for obtaining high performance contact-controlled devices (IEEE EDSK DL)
ソースゲートトランジスタ（SGT）は比較的長い歴史を持っていますが、最近になって主流の技術により、大規模に効果的に実装できるようになりました。この講演は、先進的な薄膜トランジスタを用いた効率的なアナログおよび混合信号設計に関心のある方々に向けられています。SGTは、センサーデータのエッジ処理、信号調整、電流モード駆動に向けた将来のアプリケーションへの発展的進行を提供します。重要なことに、この概念は実際にはどんな材料システムにも適用できます。したがって、この講演では、接触効果のエンジニアリングとモデリングの基本、成功するSGT実装のための設計ルール、薄膜シリコン、有機、酸化物半導体での性能最適化の特徴、そして追加機能のための構造進化について紹介します。最後に、接触制御薄膜トランジスタの進化の次のステップであるマルチモーダルトランジスタ（MMT）が簡単に紹介されます。
Source-gated transistors (SGTs) have a relatively long history of development but only recently have mainstream technologies allowed for their effective implementation at scale. This talk is addressed to those interested in efficient analog and mixed signal design with advanced thin-film transistors. They provide a development progression with a forward look toward SGT application to future edge processing of sensor data, signal conditioning, and current-mode driving. Crucially, the concept can be applied in practically any material system. As such, the talk will present the fundamentals of contact effect engineering and modelling, design rules for successful SGT implementation, specifics of performance optimisation in thin-film silicon, organic, and oxide semiconductors, and structural evolutions for additional functionality. Finally, the next step in the evolution of contact-controlled thin-film transistor, the multimodal transistor (MMT) will be briefly introduced.
Date and Time
Location
Hosts
Registration
- Date: 09 Apr 2024
- Time: 10:00 AM to 12:00 PM
- All times are (UTC+09:00) Osaka
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- NAIST (Nara Institute of Science and Technology)
- Takayama-cho, Ikoma
- Nara, Nara
- Japan 630-0192
- Room Number: F509
- Click here for Map
- Contact Event Host
-
mutsu@rins.ryukoku.ac.jp
matsuda@ele.kindai.ac.jp
- Co-sponsored by IEEE EDS Kansai Chapter
Speakers
Radu A. Sporea of University of Surrey
Key considerations for obtaining high performance contact-controlled devices
Source-gated transistors (SGTs) have a relatively long history of development but only recently have mainstream technologies allowed for their effective implementation at scale. This talk is addressed to those interested in efficient analog and mixed signal design with advanced thin-film transistors. They provide a development progression with a forward look toward SGT application to future edge processing of sensor data, signal conditioning, and current-mode driving. Crucially, the concept can be applied in practically any material system. As such, the talk will present the fundamentals of contact effect engineering and modelling, design rules for successful SGT implementation, specifics of performance optimization in thin-film silicon, organic, and oxide semiconductors, and structural evolutions for additional functionality. Finally, the next step in the evolution of contact-controlled thin-film transistor, the multimodal transistor (MMT) will be briefly introduced.
Biography:
Dr Radu Sporea is Associate Professor in Semiconductor Devices at the University of Surrey, and holds an EPSRC Early Career Fellowship (2021-2026). He was RAEng Research Fellow (2011-2016), EPSRC PhD+ Fellow (2010-2011) and PhD researcher (2006 – 2010). Radu studied Computer Systems Engineering at “Politehnica” University, Bucharest, and worked as Design Engineer for Catalyst Semiconductor Romania on ultra-low-power CMOS analog circuits. Radu was named EPSRC Rising Star in 2014 and received the I K Brunel Award for Engineering in 2015, the Vice Chancellor’s award for Early Career Teaching in 2017 and the Tony Jeans Inspirational Teaching distinction in 2018. In 2021, he was a finalist for Innovator of the Year prize at Surrey. His research focuses on advanced thin-film transistors for improved manufacturability, large area sensors and sensor arrays for smart environments, and paper-based electronics and physical-digital interaction. He is chair of the IEEE EDS UK and Ireland chapter.
Email:
Address:Address:University of Surrey, Guildford, Surrey, United Kingdom, GU2 7XH
Agenda
2024年4月9日（火） 10：00-12：00
場所：奈良先端科学技術大学院大学
物質創成科学領域 F509
ハイブリッド開催
高性能な酸化物薄膜トランジスタの設計と実証