Chiplet Design and Heterogeneous Integration Packaging

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Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have generated lots of traction lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. 



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  • Date: 26 Mar 2024
  • Time: 06:30 PM to 07:45 PM
  • All times are (UTC-05:00) Eastern Time (US & Canada)
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  • 1015 North Quincy Street
  • Arlington, Virginia
  • United States 22201
  • Building: Arlington Central Library
  • Room Number: 201 Bluemont Room

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  • Starts 20 February 2024 05:24 PM
  • Ends 26 March 2024 05:24 PM
  • All times are (UTC-05:00) Eastern Time (US & Canada)
  • No Admission Charge


  Speakers

John H Lau John H Lau of Unimicron Technology Corporation

Biography:

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 527 peer-reviewed papers (380 are the principal investigator), 52 issued and pending US patents (30 are the principal inventor), and 23 textbooks (all are the first author), e.g., Chiplet Design and Heterogeneous Integration Packaging (525 pages, Springer, 2023). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.





Agenda

6:10 PM: Networking and Refreshments

6:30 PM: Announcements and Speaker Introduction

6:35 PM: DL

7:30 PM: Questions and Answers

7:45 PM: Adjourn

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In this lecture, the following topics will be covered.

System-on-Chip (SoC)

Why Chiplet Design?

Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split

Chip partition and Heterogeneous Integration

Chip split and Heterogeneous Integration

Advantages and Disadvantages

Lateral Communication between Chiplets (e.g., Bridges)

Bridge Embedded in Build-up Package Substrate

Bridge Embedded in Fan-Out EMC with RDLs

UCIe

Hybrid Bonding Bridge

Chiplet Design and Heterogeneous Integration Packaging - Multiple System and Heterogeneous Integration

Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration)

Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration)

Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration)

Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration)

Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration)

Summary

Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging

Trends in Chiplet Design and Heterogeneous Integration Packaging

Who Should Attend?

If you (students, engineers, and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. The lectures are based on the publications by many distinguish authors and the books by the lecturer.