Two days' workshop on chip design using Cadence tools
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A two-day workshop on Chip Design using Cadence Tools was conducted by the PACE IEEE Student Branch and IEEE CEDA in the Department of ECE on February 27 and 28. The workshop was successfully completed under the coordination of Dr. Zakir B., Associate Professor. The resource person for the workshop was Mr. P Rajendra from Entuple Technologies, Bangalore.
This workshop is designed to provide participants with a comprehensive understanding of the latest advancements in chip design technology, equipping them with the skills and knowledge necessary to excel in this rapidly evolving field.

Date and Time
Location
Hosts
Registration
Speakers
Raj of Entuple Technologies Pvt. Ltd.
Topic:
Cadence Tools for VLSI Design
Workshop Highlights:
Day 1: Introduction to Cadence Tools and Basic Concepts
Overview of Cadence tool suite
Understanding the fundamentals of chip design
Hands-on experience with Cadence tools for schematic entry and simulation
Introduction to layout design and physical verification
Day 2: Advanced Topics and Practical Applications
Signal integrity and power analysis
High-speed design considerations
Introduction to analog and mixed-signal design
Case studies and real-world applications, finally
Q&A and interactive sessions.
Email:
Address:Indiranagar, , Bangalore, India, 560038
Agenda
Workshop Highlights:
Day 1: Introduction to Cadence Tools and Basic Concepts
Overview of Cadence tool suite
Understanding the fundamentals of chip design
Hands-on experience with Cadence tools for schematic entry and simulation
Introduction to layout design and physical verification
Day 2: Advanced Topics and Practical Applications
Signal integrity and power analysis
High-speed design considerations
Introduction to analog and mixed-signal design
Case studies and real-world applications, finally
Q&A and interactive sessions.
Media
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