Advanced Short Course on "All-Digital Phase-Locked Loops (ADPLL)"


Dean of AGH University's Faculty of Electrical Engineering, Automatics, Computer Science and Biomedical Engineering together with Department of Measurement and Electronics and IEEE Solid-State Circuit Society Chapter Poland invites for an ADVANCED SHORT COURSE:

Advanced Short Course on “All-Digital Phase-Locked Loops (ADPLL)”.

Prof. Bogdan Staszewski (University College Dublin, Ireland).

The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using ”free” but powerful digital logic.

  Date and Time




  • AGH University of Science and Technology
  • Av. Mickiewicza 30
  • Cracow, Malopolskie
  • Poland 30-059
  • Building: B-1
  • Room Number: 121

  • Starts 21 November 2016 02:43 PM
  • Ends 08 December 2016 01:37 AM
  • All times are Europe/Warsaw
  • No Admission Charge
  • Register


Prof. Robert Bogdan Staszewski


All-Digital Phase-Locked Loops


Robert Bogdan Staszewski has completed Technikum Elektryczne in Białystok. He received his B.Sc. (summa cum laude), M.Sc. and Ph.D. degrees, all in Electrical Engineering, from the University of Texas at Dallas, Dallas, USA, in 1991, 1992 and 2002, respectively. From 1991 to 1995, he was with Alcatel Network Systems in Richardson, Texas, USA, working on SONET cross-connect systems for fiber optics communications. He joined Texas Instruments, Dallas, TX, USA, in 1995 where he was elected Distinguished Member of Technical Staff (limited to 2% of technical staff). Between 1995 and 1999, he was engaged in advanced CMOS read channel development for hard disk drives. In 1999, he co-started a Digital RF Processor (DRP) group within Texas Instruments with a mission to invent new digitally intensive approaches to traditional RF functions for integrated radios in deeply-scaled CMOS processes. He was appointed a CTO of the DRP group between 2007 and 2009. In July 2009, he joined Delft University of Technology, Delft, The Netherlands, where he is currently a part-time Full Professor. Since Sept. 2014, he has been a Professor with University College Dublin (UCD), Dublin, Ireland. He has authored and co-authored three books, five book chapters, 210 journal and conference publications, and holds 160 issued US patents. He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award.

Prof. Robert Bogdan Staszewski


All-Digital Phase-Locked Loops



AGH University of Science and Technology, Building B-1, room: 121 lecture hall

Day 1: 8th december 2016:

- All-Digital Phase-Locked Loop (ADPLL) [3 lectures: 8:00 - 9:30, 10:00 - 11:30, 12:00 - 13:30]

Day 2: 9th december 2016:

- Digitally-controlled oscillator (DCO) [2 lectures: 8:00 - 9:30, 10:00 - 11:30]

- Time-to-digital converter (TDC) [1 lecture: 12:00 - 13:30]

Recommended Literature: Book: R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New Jersey: John Wiley & Sons, Inc., Sept. 2006. ISBN: 978-0471772552.