IEEE Santa Clara Valley Reliability Chapter November Meeting

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in MOSFET/FinFET electrical characteristics is addressed. A physics-based compact modeling methodology for multi-scale simulation of all contributing components of stress induced variability is described. A simulation flow that provides an interface between layout formats (GDS II, OASIS), and FEA-based package-scale tools, is developed. The EDA tool-prototype, developed on the basis of proposed methodology, can be used to optimize the floorplan for different circuits and packaging technologies, and/or for the final design signoff, for all stress induced phenomena. A calibration technique based on fitting to measured electrical characterization data is presented, along with correlation of the electrical characteristics to direct physical strain measurements. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.