Masum Hossain - Short Course on High-Speed Interfaces (IEEE SSCS Chapter Poland)

#IC #CMOS #SerDes #Jitter #Wireline

Digital equalization for Multilevel signaling in high-speed SerDes

Multilevel signaling has extended the lifeline of wireline signaling beyond 100 Gb/s. But it’s SNR penalty has mandated much more sophisticated equalization that is more suitable for digital implementation. This presentation aims at bridging the gap between well-understood analog/mixed-signal solutions and today’s DSP-based solutions. Starting from traditional analog architectures, this talk will walk through the evolution toward today’s DSP-based equalization and provide the background for tomorrow’s sequence decoding.

Evolution of the Timing Recovery techniques in High-speed Links

Timing recovery techniques have evolved significantly over the last 25 years of high-speed link design. In the first decade, this evolution was motivated by technology scaling and scalability, where it gradually moved to a fully digital implementation from an analog PLL-based approach. However, the evolution in the last decade is motivated by the adoption of multilevel signaling. The emergence of MMSE as an alternative to 2X oversampled solutions is an example of such recent developments. This talk aims to bring designers up to speed on the state-of-the-art ADC-DSP solutions, explain their motivation, and finally conclude with silicon results to validate the performance improvement achievable in these architectures.

Low-jitter flexible frequency generation for next-generation communication systems

The next-generation wireline and wireless systems promise wider bandwidth to enable a vast range of applications, including autonomous vehicles, virtual reality, and the internet of things. Such high data rates mandate precise clock generation to meet the timing budget. At the same time, flexibility to support multiple standards and scalability to meet higher integration density introduces additional dimensions to the clocking challenge. This talk will discuss recent circuit and architecture innovations to address these challenges. Starting from simple phase-locking concepts such as PLL, DLL and ILO, this talk will explain how the combination of these techniques is adopted in modern communication systems. It will also describe two example cases - i. A 28 GHz frequency synthesizer for 5G LO based beam forming, and ii. A flexible clocking solution for 10Gb/s to 112 Gb/s SerDes in 7 nm finFET technology.

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• AGH University of Kraków
• Av. Mickiewicza 30
• Krakow, Malopolskie
• Poland 30-059
• Building: C-6 (Centrum Energetyki)
• Room Number: 307/308

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• Digital equalization for Multilevel signaling in high-speed SerDes (13:30 - 14:45)

  Evolution of the Timing Recovery techniques in High-speed Links (15:00 - 16:15) 

  Low-jitter flexible frequency generation for next-generation communication systems (16:30 - 17:45)

   

• Co-sponsored by Silicon Creations

• Link to External Registration