Analog/Mixed-Signal Design in FinFET With Dr. Alvin Loke

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Date and Time:  Wednesday, 31 May 2017, Networking 6:30pm-7pm, technical talk 7-8 pm, and career coaching session 8pm to 8:30pm 

Cost: Free to IEEE, Qualcomm and students with ID; all others $5 cash only at the door.

 


Presented by the IEEE San Diego Young Professionals 

ABSTRACT

Continued consumer demand for mobile ICs has propelled CMOS scaling to arrive at the finFET with foundry offerings starting at 16/14 nm. The compact 3-D structure of the finFET offers superior short-channel control that achieves digital power reduction and adequate device performance. As SoC technology remains dictated by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must adapt to new design constraints. We attempt to summarize the challenges and considerations faced when porting analog/mixed-signal designs to finFET. At 16/14 nm, designers must also cope with many accumulated implications of earlier scaling innovations leading to the finFET.

In addition, the IEEE San Diego Young Professionals Section is offering a Young Professionals & Students career coaching session after the talk and a Q&A 



  Date and Time

  Location

  Contact

  Registration



  • Qualcomm Technologies
  • 10155 Pacific Heights Blvd
  • San Diego, California
  • United States 92121
  • Building: Building AZ Multipurpose room A/B/C
  • Click here for Map

Staticmap?size=250x200&sensor=false&zoom=14&markers=32.9032558%2c 117
  • IEEE San Diego Section: www.sdieeee.org

     

  • Starts 09 May 2017 12:00 AM
  • Ends 31 May 2017 04:00 PM
  • All times are America/Los_Angeles
  • No Admission Charge
  • Register


  Speakers

Alvin Loke of Qualcomm

Topic:

Analog/Mixed-Signal Design in FinFET With Dr. Alvin Loke

ABSTRACT


Continued consumer demand for mobile ICs has propelled CMOS scaling to arrive at the finFET with foundry offerings starting at 16/14 nm. The compact 3-D structure of the finFET offers superior short-channel control that achieves digital power reduction and adequate device performance. As SoC technology remains dictated by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must adapt to new design constraints. We attempt to summarize the challenges and considerations faced when porting analog/mixed-signal designs to finFET. At 16/14 nm, designers must also cope with many accumulated implications of earlier scaling innovations leading to the finFET.


BIOGRAPHY


Alvin Loke received a B.A.Sc. in engineering physics from the University of British Columbia, and M.S. and Ph.D. in electrical engineering from Stanford. He worked on CMOS process integration for several years at HP Labs and on assignment at Chartered Semiconductor. Since 2001, he has been designing circuits for a variety of wireline links and addressing next-generation CMOS analog/mixed-signal concerns at Agilent and Advanced Micro Devices in Fort Collins, CO, and most recently at Qualcomm in San Diego, CA. He has authored several dozen publications and holds 19 US patents. Alvin has served as Technical Program Committee member of CICC, IEEE Chapter Chair, Guest Editor of the IEEE Journal of Solid-State Circuits, Industrial Advisory Board member at Colorado State University, and IEEE Distinguished Lecturer.

Alvin Loke of Qualcomm

Topic:

Analog/Mixed-Signal Design in FinFET With Dr. Alvin Loke

Biography:

Address:San Diego, United States





Agenda

6:30 - 7:00 Networking and refreshments

7:00 - 8:00 Talk

8:00- 8:30 Career coaching and Q&A